Total 114 job vacancies by Sandisk

ESSENTIAL DUTIES AND RESPONSIBILITIES:

We’re hiring a Sr. Operational Technology Security Engineer (OT) to manage Sandisk’s OT visibility and resilience program across high‑technology manufacturing sites. You’ll stand up and mature our OT monitoring solution, integrate telemetry into our SIEM, and partner with factory operations to ensure security without disrupting production.

This role owns engineering, delivery, and ongoing operations of OT security—bridging engineering, manufacturing, and the SOC—so that Sandisk maintains continuous production with zero downtime due to internal cybersecurity incidents.

• Program Partnership: Assist in defining and executing the OT security roadmap, aligning with corporate cybersecurity strategy and manufacturing uptime objectives.
• OT Monitoring Deployment: Manage installation and configuration of OT monitoring platforms such as Nozomi Networks, Claroty, Dragos, Armis, ensuring proper sensor placement for maximum visibility.
• Traffic Analysis & Protocol Coverage: Implement tools for deep packet inspection and protocol analysis (e.g., Wireshark, Zeek, Suricata) to monitor Modbus, Profinet, DNP3, OPC-UA, and other industrial protocols.
• SIEM Integration: Collaborate with SOC and architecture teams to stream OT telemetry into SIEM/SOAR platforms, develop detection logic, and optimize alerting to reduce false positives.
• Asset & Risk Management: Establish and maintain a comprehensive OT asset inventory, vulnerability management process, and configuration baselines for critical systems.
• Network Segmentation & Access Control: Participate in segmentation projects, firewall rule reviews, and identity separation between IT and OT environments; implement secure remote vendor access protocols.
• Incident Response & Resilience: Participate in creating OT-specific incident response playbooks, conduct tabletop exercises, and ensure disaster recovery plans meet manufacturing continuity requirements.
• Compliance & Standards: Ensure adherence to NIST CSF, IEC 62443, and corporate security policies; prepare for internal and external audits.
• Cross-Functional Collaboration: Work closely with onsite IT teams and Manufacturing leadership to schedule changes, minimize production impact, and jointly achieve zero-downtime objectives.
• Metrics & Reporting: Manage KPIs (e.g., telemetry coverage, MTTR, segmentation compliance) and deliver executive-level reporting on OT security posture.

Job Description:

We need an Firmware verification engineers who understand UFS/eMMC embedded NAND system design and firmware algorithms in order to create a firmware design verification plans and implement them in modern object oriented languages.

• Work closely with the system architects and the firmware team to develop design verification plans, test bench and test cases
• Develop an overall firmware validation strategy including defining validation infrastructure and validation methodology
• Debug the firmware and expose design issues
• Design functional tests required to meet customer needs
• Review SanDisk UFS/eMMC embedded NAND validation requirements and influence future SanDisk product design for debug and test
• Work with customers to understand field bugs and to enhance the validation coverage
• Interface with all key stakeholders to ensure product validation meets customer expectations and needs

Technical and analytical skills required

• Familiar with firmware development, Integration and validation
• Knowledgeable on product and quality standards and relevant host protocols, in particular eMMC and UFS.
• Test coverage methods for real-time embedded systems, especially storage systems and/or NAND storage
• Able to methodically root cause complex failure mechanism
• Strong programming knowledge & debugging skills in Python, C and C++.

• Soft skills, Excellent written and verbal skills, be a Team player
• Able to develop key relationships
• Able to elect requirements from all stakeholders
• Be able to work in pressure for quick resolution and delivery.

Job Description:

We need an Firmware verification engineers who understand UFS/eMMC embedded NAND system design and firmware algorithms in order to create a firmware design verification plans and implement them in modern object oriented languages.

• Work closely with the system architects and the firmware team to develop design verification plans, test bench and test cases
• Develop an overall firmware validation strategy including defining validation infrastructure and validation methodology
• Debug the firmware and expose design issues
• Design functional tests required to meet customer needs
• Review SanDisk UFS/eMMC embedded NAND validation requirements and influence future SanDisk product design for debug and test
• Work with customers to understand field bugs and to enhance the validation coverage
• Interface with all key stakeholders to ensure product validation meets customer expectations and needs

Technical and analytical skills required

• Familiar with firmware development, Integration and validation
• Knowledgeable on product and quality standards and relevant host protocols, in particular eMMC and UFS.
• Test coverage methods for real-time embedded systems, especially storage systems and/or NAND storage
• Able to methodically root cause complex failure mechanism
• Strong programming knowledge & debugging skills in Python, C and C++.

• Soft skills, Excellent written and verbal skills, be a Team player
• Able to develop key relationships
• Able to elect requirements from all stakeholders
• Be able to work in pressure for quick resolution and delivery.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Be part of Product & Test Engineering team responsible for engineering and manufacturing support of industry-leading SATA and NVMe Solid-StateDrive.
• SSD test program validation, failure analysis, cost reduction and yield improvements.
• Provide NPI and HVM production support for SSD test development, manufacturing flow improvement, QC failure and RMA DPPM reduction.
• Engineering support for SSD products after transition from design to high volume production, work with design, process, validation and reliability engineers to solve problems.
• Work closely with contract manufacturing and corporate internal R&D teams such as Nand, ASIC, Validation, and Firmware to develop and verify proper HVM friendly manufacturing test process.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Product Quality Oversight and Failure Analysis:
  • Lead Outgoing Quality Assurance (OQA) and Ongoing Reliability Test (ORT) monitoring, proactively identifying quality trends and resolving anomalies to ensure high product reliability.
  • Conduct in-depth failure analysis, root cause investigation, and corrective action implementation to improve overall product quality.
• Test Flow and Program Optimization:
  • Define, enhance, and maintain SSD product quality test flows, ensuring they align with industry best practices and company standards.
  • Develop and optimize automated quality test programs to improve efficiency and reliability in testing procedures.
• Performance and Reliability Reporting:
  • Oversee the creation and maintenance of product performance and reliability reports, providing key stakeholders with insights for continuous improvement.
  • Collaborate with cross-functional teams to present quality findings and drive data-driven decision-making.
• Advanced Data Analysis and Automation:
  • Perform complex data analysis to identify product quality trends, using statistical methods and machine learning models where applicable.
  • Develop and maintain automation scripts to streamline data processing, testing, and reporting workflows.
• Technical Leadership in SSD Reliability:
  • Provide technical guidance on SSD failure mechanisms, endurance, and reliability testing methodologies.
  • Collaborate with R&D, firmware, and manufacturing teams to drive quality improvements and reliability enhancements.
• Cross-Functional Communication and Issue Resolution:
  • Lead technical discussions with internal and external stakeholders, ensuring efficient resolution of quality and reliability issues.
  • Act as a liaison between engineering, manufacturing, and customer support teams to ensure alignment on product quality expectations.

ESSENTIAL DUTIES AND RESPONSIBILITES:

• Responsible for Known Good Die (KGD) wafer-level flash memory test program development, failure analysis, and debug.
• Manage production support engineering for specific products or product families after transfer from design to high-volume manufacturing.
• Interface with design, process, test, and reliability engineering teams to identify and resolve technical issues.
• Sustain and improve existing products through cost reduction initiatives and yield enhancement.
• Define correct test conditions and develop test flows to meet volume production testing requirements for advanced memory devices.
• Plan and execute product evaluation and design of experiments (DOE) focused on reliability, DPPM reduction, and die sort yield improvement.
• Perform test time analysis to optimize test methods for cost efficiency while maintaining strict quality standards.
• Develop and implement test strategies to enable rapid ramp-up of new products into high-volume manufacturing.
• Collaborate with global new product definition teams and lead assigned projects to support the successful introduction of new products to market.

We are looking for technically sound and highly skilled Analog/High Speed DDR IO Layout designer with 8-12 years of experience. The ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems.

Key Responsibilities:

• Develop and optimize MSIP IC layouts in TSMC 3nm, ensuring high performance and manufacturability.
• Collaborate with design engineers to understand design requirements and translate them into precise layouts.
• Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently.
• Work closely with the physical design team to integrate custom blocks into the overall chip design.
• Identify and resolve layout-related issues, providing creative solutions to meet design specifications.
• Conduct design reviews and provide technical feedback to improve layout practices and methodologies.
• Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes
• Any prior AI knowledge/experience which can improve Layout development effort and QoR is a big plus

Qualifications

• 8-12 years of experience in Analog/High Speed DDR IO IC layout design.
• Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics.
• Hands-on experience with custom layout design for Analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, High speed DDR IOs.
• Familiarity with custom digital layout (i.e. high speed logic paths).
• Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding).
• Strong understanding of analog/IO design principles, including circuit performance and parasitic effects.
• Aware of layout techniques to mitigate ESD, latch-up issues.
• Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below.
• Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating.
• Experience with layout optimization for power, performance, and area (PPA) metrics.
• Excellent problem-solving skills and attention to detail.
• Effective communication and teamwork abilities.

Preferred Skills:

• Knowledge of scripting languages (e.g., Skill,TCL and SVRF) for automation tasks.

• Work as one of  the senior team members or as lead of analog IPs and deliver analog blocks on-time with state-of-the-art architecture to meet the overall product requirements
• Work closely with team in designing and delivering analog blocks
• Design analog modules from scratch
• Handling assigned tasks independently
• Pro-actively get design issues/problems resolved
• Contribute to or propose innovative design solutions and design methodologies
• Work closely with the layout engineers on providing requirements and guidelines

• Development of C++/SystemC models for complex ASIC IPs, SOCs and Flash Memories.
• Create System Level Tests and/or Standalone Unit Tests and verify the models.
• Lead and Guide team in the project activities.
• Keen on schedule and quality of the deliverables.
• Timely support to the stakeholders enabling software bring-up.