Total 562 Senior Executive engineering job vacancies in Australia

Job Description:

- Preparation and filing of reports

- ⁠Review of reports

- ⁠Coordination with client on after sale services

- ⁠Preparation of quotation

- ⁠Carry out site survey

Requirements:

- Background in engineering preferred

- ⁠Proficient in autocad

- ⁠Able to work independently

- Add in the usual skills for MS office and things like work under pressure, fast pace etc.

We are seeking a Business Support Executive to provide comprehensive support to senior management, with a strong focus on budget reporting, management updates, and business operations support. This role goes beyond traditional administrative work — you will be actively involved in preparing business reports, coordinating management updates, and ensuring smooth communication across teams.

• Prepare budget reports, tracking expenses, and compiling updates for management.
• Coordinate executive meetings, including agendas, materials, logistics, and follow-ups.
• Manage schedules, correspondence, and preparing briefing decks for senior management.
• Maintain documentation and reporting systems to ensure smooth business operations.

Requirements:

• Diploma or degree in Business Administration or equivalent.
• Proven experience in business/management support in the Construction/Engineering sector.
• Strong skills in MS Excel and PowerPoint, with hands-on experience preparing reports and presentations.
• Excellent communication, organizational skills, and ability to work independently.

If you are keen to apply for the position, kindly email your detailed resume in MS Word to hr@recruit-expert.com

Please note that only shortlisted candidates will be notified.

For more job opportunities, please visit our website at www.recruit-expert.com

EA Licence: 19C9701

Registration: R1326740

Company Overview

Aeta Engineering Pte Ltd is led by senior personnel with over 40 years of combined experience. We provide turnkey M&E engineering solutions focused on semiconductors, electronics, data centers, pharmaceuticals, food, and fragrance industries, driven by innovation and sustainability.

Job Summary

Supervise on-site Mechanical & Electrical installation projects, ensuring compliance with client requirements, safety standards, and project specifications while coordinating with stakeholders to deliver quality engineering solutions.

Responsibilities

• Supervise on-site Mechanical & Electrical installation projects to ensure adherence to project specifications and quality standards
• Collaborate with Project Manager/Engineer to prepare Work Method Statements, Risk Assessments, and related client documentation
• Interpret Mechanical and Electrical schematic drawings to guide installation and troubleshooting activities
• Analyze and apply client requirements to plan and execute site works effectively
• Prepare and submit project-related documents to clients accurately and timely
• Coordinate and liaise with subcontractors, suppliers, vendors, and clients to ensure smooth project execution
• Monitor installation progress and prepare detailed weekly and monthly progress reports
• Enforce site safety protocols and ensure compliance with all safety regulations
• Compile and prepare testing documentation as requested by Project Manager or Engineer for project scope verification
• Perform additional duties assigned by superiors to support project delivery

Step into a career with ASM, where cutting edge technology meets collaborative culture. ​

For over 55 years ASM has been ahead of what’s next, at the forefront of innovation and what’s technologically possible. With more than 4,500 ASMers representing 70 nationalities, our people and our advanced semiconductor devices are playing a crucial role in trends such as 5G, cloud computing, AI, and autonomous driving.  But we’re more than just a tech company. We value diversity, inclusion and sustainability as we strive to make a positive impact on the world.  Our development programs help support your growth, shaping your future and pushing the boundaries of innovation to unleash potential.  

Job's mission

Join ASM’s Advanced Packaging team and lead the design and development of next-generation semiconductor process equipment. In this role, you will shape system architecture, drive automation strategies, and collaborate across functions to deliver innovative solutions. Your expertise will ensure projects meet the highest standards of safety, quality, and performance.

What you will be working on

• Lead design and development of semiconductor vacuum systems, including equipment selection, process controls, and automation integration.
• Develop and implement automation strategies using PLCs, SCADA, and related tools to optimize efficiency.
• Manage project timelines, budgets, and resources while ensuring compliance with safety and quality standards.
• Collaborate with cross-functional teams in manufacturing, operations, and quality to align on goals and deliverables.
• Provide technical support and troubleshooting for equipment and automation systems, driving root cause analysis and resolution.
• Own BOM release and maintenance, ensuring accurate documentation and reporting for stakeholders.
• Drive continuous improvement initiatives and stay current with industry trends and emerging technologies.
• Apply engineering principles and research data to create designs for semiconductor systems and products.
• Perform engineering calculations for structural, thermal, and fluid dynamics challenges.
• Create and revise CAD models and detailed drawings using Creo Parametric for components and assemblies.
• Prepare comprehensive design documentation for manufacturing and testing of prototypes and production products.

What we are looking for

• Bachelor's, Master’s or PhD in Mechanical Engineering or related field.
• Minimum 8 years of experience in semiconductor equipment design, development, and automation.
• Expertise in complex mechanical systems such as reactors, vacuum chambers, gas delivery systems, pneumatics, and cooling circuits.
• Strong analytical and problem-solving skills with ability to lead innovative design concepts.
• Experience with PLC programming and revision control tools such as Git.
• Ability to work independently and collaboratively in a team environment.

What sets you apart

• Experience with semiconductor capital equipment and metal deposition products.
• Knowledge of CE, NFPA, Semi S2-95, and other relevant standards for semiconductor manufacturing equipment.
• Familiarity with materials including metals, plastics, coatings, and finishes.
• Proficiency in Microsoft applications, CREO, and AutoCAD.
• Knowledge of ASME Y14.5 and/or ISO 1101:2017 geometric dimensioning and tolerancing.
• Strong communication skills to present design concepts effectively to peers and management.
• Ability to manage multiple priorities and meet aggressive deadlines while maintaining quality standards.

Apply today to be part of what’s next.

We make the tech that enables the chips in devices which improve lives around the world. We do this with an eye to the future, pushing the boundaries of what’s possible through cutting-edge innovation, and driving the next wave of technological breakthroughs that shape how we live, work, and connect.

To learn more about ASM, find us at asm.com and on LinkedIn, Facebook, Instagram, X and YouTube.

ASM is an equal opportunity employer and considers qualified applicants for employment without regard to race, color, religion, age, nationality, social or ethnic origin, sexual orientation, gender, gender identify or expression, marital status, pregnancy, political affiliation, disability, genetic information, veteran status, or any other characteristic protected by law.

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.
  

  Performs hardware, software, semiconductor design or telecomm engineering assignments. This job mapping should be used only if the position cannot be mapped specifically to other design/development engineering jobs.

Key Responsibilities:

• Carry out daily inventory store activities;
• Receive, inspect, and verify incoming materials, goods, and supplies against delivery documentation;
• Issue materials and products in accordance with authorized requests and record all stock movements;
• Work with inventory store manager-in-charge to review process workflow and implement process improvements to increase efficiency and effectiveness;
• Ensure safe, proper and effective housekeeping of inventory store;
• Issue items, update inventory and monitor stock levels;
• Manage disposal of waste and carry out regular inspections of inventory store items and storage conditions;
• Label, store and file stock items and ensure all required documentation are completed;
• Conduct regular stock takes, support reconciliation and compile necessary reports;
• Allocate storage space and ensure safe equipment handling at all times;
• Participate in innovation and work improvement projects;
• Perform any other duties as assigned.
  

The ideal candidate should preferably:-

• Possess at least Nitec/Higher Nitec qualifications; and
• Be willing to perform shift work.

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.

Job Purpose

Intercontinental Exchange, Inc. (ICE) offers a unique opportunity to work on cutting-edge technology and complex business challenges in the financial sector. The Senior Network Engineer role within the ICE Network Engineering team provides technical leadership across network design, validation, deployment, maintenance, and operational support.

The successful candidate will help advance one of the world’s largest global financial networks, supporting a broad portfolio of mission-critical services. This role requires the ability to thrive in a dynamic, team-based global environment, demonstrating strong problem-solving, sound decision-making, and a high degree of professionalism.

Responsibilities

• Design, configure, and implement complex Juniper- and Arista-based data centre and WAN solutions that support real-time market data and multicast services, with an emphasis on ultra-low latency, resilience, and reliability.
• Collaborate with cross-functional teams to gather business and technical requirements and translate them into scalable, effective network designs.
• Support and maintain a range of multi-vendor production network environments that are critical to business operations.
• Develop and maintain high-quality network documentation, including diagrams, configurations, standards, and operating procedures.
• Provide expert-level troubleshooting and escalation support for network incidents and outages, restoring service quickly and minimizing operational impact.
• Stay current with industry trends, emerging technologies, and best practices related to WAN, data centre, and low-latency network engineering.
• Understand and follow ICE operational policies and procedures and actively promote adherence to them across day-to-day engineering activities.
• Provide the technical expertise required to ensure network changes are planned, validated, and executed safely, effectively, and efficiently.
• Work closely with vendors, service providers, and internal technology teams to deliver seamless, high-performance network solutions.

Knowledge and Experience

• Bachelor’s degree in computer science, Information Technology, or a related field.
• Must hold a current Juniper and/or Cisco professional-level certification.
• 7+ years of networking experience, including at least 5 years designing, configuring, and implementing complex Juniper-based global MPLS WAN networks.
• In-depth knowledge of WAN protocols and technologies, including BGP, IS-IS, OSPF, MPLS, VPLS, VPNs, and QoS.
• Extensive knowledge of two or more network operating systems or platforms, including Junos, IOS/NX-OS, EOS, or F5 LTM/GTM.
• Extensive knowledge of Check Point FW-1, Palo Alto, or similar stateful packet inspection firewalls.
• Deep understanding of TCP/IP, NAT, route maps, access control lists, and routing policies.
• Extensive hands-on experience with Juniper networking products, including Junos OS, MX Series routers, EX/QFX Series switches, and SRX Series firewalls.
• Extensive knowledge of multicast network design and troubleshooting, including IGMP and PIM protocols.
• Demonstrated ability to distinguish between critical business-impacting incidents and minor issues, and to resolve or escalate them appropriately.
• Understanding of low-latency network design principles, clock synchronization, and Precision Time Protocol (PTP) implementations.
• Strong knowledge of Python and experience using it for network automation and operational efficiency.
• Strong knowledge of modern configuration management and automation tools, including Ansible, Jinja, and JSON.
• Experience with network monitoring and management tools, together with strong packet capture and analysis skills.
• Thorough understanding of Linux shell commands and experience with network automation tools and frameworks.
• Ability to adapt to a fast-paced, evolving global environment while staying current with advancements in networking technology.

Personal Attributes

• Strong verbal and written communication skills, with a customer-focused approach.
• Self-motivated, with the ability to work independently and take ownership of outcomes.
• Able to manage multiple priorities and work effectively across concurrent projects.
• Professional, collaborative, and service-oriented in approach.

Schedule

• This role is office-based, with attendance required five days per week.
• Some weekend and after-hours work will be required to support operational and change activities

As a Senior Mechanical Engineer, you will lead the design and standardization of mechanical systems for next-generation data centers. You will own the development of Reference Designs for hyperscale and retail product tracks, ensuring scalability, cost efficiency, and compliance with global standards.

This role is pivotal in shaping advanced mechanical infrastructure solutions that enable hyperscale growth, high-density and liquid-cooled deployments, and future-ready data center designs—while ensuring uncompromising reliability, efficiency, and sustainability, and leading continuous improvement initiatives in partnership with Operations and Construction teams.

Key responsibilities

· Develop and maintain mechanical HVAC Reference Designs for hyperscale and retail data center product offerings, including liquid cooling and air-based systems.

· Design resilient, scalable HVAC mechanical systems such as chilled water loops, CDUs, piping, and heat rejection systems for high-density environments.

· Define and analyze piping and pipe supports to meet industry standards and regulatory requirements.

· Ensure compliance with regional mechanical codes and internal standards.

· Collaborate with Design Delivery & Construction teams to localize designs and ensure constructability.

· Partner with Operations to identify improvement opportunities and implement design enhancements for reliability and maintainability.

· Conduct root cause analysis and implement corrective actions for mechanical system issues.

· Drive innovation and R&D for emerging technologies (e.g., liquid cooling integration, modular mechanical systems).

· Work with global suppliers and manufacturers to specify appropriate cooling equipment and assemblies.

· Produce clear technical documentation: design specifications, schematics, and white papers.

· Lead technical forums and provide subject matter expertise across regions

· Actively champion and implement policies and procedures for occupational health & safety in the workplace, information security management, environmental management systems; incident management; and comply with all legal regulatory requirements of the organization

The successful candidate:

· Bachelor’s degree in Mechanical Engineering or related discipline

· 10+ years of experience in heavy industrial environments including 5+ years in mission-critical facilities

· Preferred Professional Engineer (PE) or Chartered Engineer certification.

· Experience designing piping and plumbing systems for cooling in data centers.

· Prior experience executing product designs from concept to production, including specification, prototyping, validation, and testing.

· Knowledge of air- and water-cooled systems for high-heat density applications.

· Familiarity with medium-temperature chilled water systems, CDUs, and liquid cooling integration.

· Understanding of industry standards (ASME B31.1 & B31.3) and mechanical codes.

· Ability to research and implement new designs and technologies from concept through deployment.

· Experience managing supplier relationships and conducting factory acceptance tests.

· Preferred proficiency with modelling software tools (e.g., AutoCAD, Revit, BIM)

About our group:

Media new product launch is to provide technical solutions to new product qualification, product yield, quality and reliability through developing new process and metrology. The team also needs to work closely with media R&D group and drive design center to continue optimize media process in order to meet product electrical recording performance as well as mechanical, tribology, manufacturability. Internally, the team need to work with different functional groups to deliver new mag design in very dynamic and challenging environment. 

About the role - you will:

Reporting to the Engineering Director, the incumbent will:

• Develop on HAMR sputter process to improve media ADC and mechanical performance to meet new product timeline.
• Design of experiment to understand the process window/margin.
• Good understanding of recording physics.
• Work with cross functional team on new alloys/process related defect issues.
• Transfer new product process into mass production and continue improve process to meet customer requirement.
• Technical lead of sputter projects.

About you:

Key characteristics defining outstanding candidates:

• Good understanding on magnetic recording materials, process and thin film technology.
• Teamwork and self-motivated.
• Fast learning capability.
• Strong communication and technical leadership skills.
• Ability to drive technical innovation into rapid product solutions.
• Flexibility and excellent time and task management capabilities.

Your experience includes:

• Master or Ph.D degree in Material science, magnetic recording physics or related engineering disciplines.
• Knowledge and skills in any of these areas – Material science, HAMR knowledge, thin film sputter process.
• R&D in magnetic recording media process, including process DOE, magnetic characterization tools, and data analysis techniques are all skills that will be beneficial in this role.
• Proficient in English speaking and writing.

As a Senior Electrical Engineer, you will lead the design and standardization of electrical infrastructure for next-generation data centres. You will own the development of Reference Designs for hyperscale and retail product tracks, ensuring scalability, cost efficiency, and compliance with global standards.

This role is pivotal in shaping advanced electrical infrastructure solutions that enable hyperscale growth, high-density and liquid-cooled deployments, and future-ready data center designs—while ensuring uncompromising reliability, efficiency, and sustainability, and leading continuous improvement initiatives in partnership with Operations and Construction teams.

Key responsibilities

• Develop and maintain electrical Reference Designs for hyperscale and retail data center product offerings.
• Design resilient, scalable electrical distribution systems and substation solutions for high-density environments.
• Ensure compliance with regional electrical codes and internal standards.
• Conduct engineering analysis, feasibility studies, and value engineering for cost and performance optimization.
• Collaborate with Design Delivery & Construction teams to localize designs and ensure constructability.
• Partner with Operations to identify improvement opportunities and implement design enhancements for reliability and maintainability.
• Review and approve critical equipment submittals, including vendor FATs and acceptance tests.
• Partner with suppliers and manufacturers to specify and qualify electrical equipment.
• Conduct root cause analysis and implement corrective actions for electrical system issues.
• Drive innovation and R&D for emerging technologies (e.g., liquid cooling integration, advanced monitoring).
• Produce clear technical documentation: design specifications, schematics, and white papers.
• Lead technical forums and provide subject matter expertise across regions.
• Actively champion and implement policies and procedures for occupational health & safety in the workplace, information security management, environmental management systems; incident management; and comply with all legal regulatory requirements of the organization

Thesuccessful candidate:

·       Bachelor’s degree in Electrical Engineering or related discipline

·      10+ years of experience in heavy industrial or commercial electrical design, including 5+ years in mission-critical facilities

·      Strong understanding of regional electrical codes (IEC, NEC, CCC, etc.)

·      In-depth knowledge of critical data center electrical systems, including:

-       Medium-voltage distribution systems.

-       UPS systems, diesel generators, electrical switchgear, PDUs, VFDs, and ATS/STS.

-       High voltage substations

·      Experience with controls systems and integration

·      Proven ability to research and implement new designs and technologies from concept through deployment

·      Experience managing supplier relationships and conducting factory acceptance tests

·      Proficiency with modelling software tools (e.g., AutoCAD, Revit, BIM)

As Frontend Central Product Integration Engineering and transformative (CPIE) team at Micron Technology, Inc., you will be leading new initiatives to deliver pioneering process capability, best-in-class bits per wafer (Yield) with the highest quality and fastest speed through innovation and collaboration with multi-functional teams. Your primary focuses include but not limited to:

Initiate new data solutions and methodologies to:

• identify process, test, and design improvement opportunities, specialized in UE_ROW & all quality index, Front End-PTS integration, and high-value-bits (PG2+) yield;

• modeling, monitoring and aiming for tool performance benchmarking;

• Process equipment prognostics and process integration optimization;

• Identity test optimization opportunities for high product grade yield improvement.

• Collaborate with site Process & Equipment Engineering, Manufacturing(MFG), Product Integration Engineering (PIE) and Data Science (DS) team to establish feasibility of new initiatives, demonstrate business values, and prototype solution mock-ups;

• Partner with Global Quality (GQ), Product Engineering (PE), Central PEE(CPEE), Smart Mfg Artificial Intelligent (SMAI), Technology Development (TD), and Suppliers to deliver end to end solutions, implement BKM development and deployment to production.

• Integrates AI-assisted tools and insights into daily work to improve efficiency, quality, or effectiveness,exercising sound judgment and complying with organizational standards and legal requirements.

• Contributes to a culture of continuous improvement by identifying, testing, and sharing AI-enabledenhancements within one’s scope of work.

Collaboration

• Partner closely with multi-functional teams to ensure successful communication and collaboration for project implementation.

• Detail oriented with the ability to work independently

• Dependability and able to work effectively in multi-functional teams.

• Facilitate and lead activities in designing and optimizing current system, methods, tool, skill to be Best In industry.

• Manage priorities and enhancements to improve business processes and existing systems that are global in nature.

• Willing to work during non-standard hours when needed to provide support to engineering teams at any Micron site.

• Strong growth mindset and willing to continue to learn, unlearn, relearn.

Communication

• Effective communication skills in verbal/written.

• Self-motivated. Able to work independently with minimal supervision.

• Able to travel as required to support department and company objectives.

Requirement and Technical Competency:

• Experience in PIE, Test solution team, product engineering and circuit design engineering. Understanding of Process/Product Integration will be advantageous;

• In depth knowledge of processes, equipment and control system;

• Proficiency in data analytical tools such as Y3, JMP, Python to perform numerical experiment. Proficiency in Statistical/Machine Learning will be additional advantageous; 

• Proven track record to make decisions, multi-task, and solve problems and address root causes.

• Exhibit critical thinking to find opportunities.

• PhD/Masters/Bachelors with relevant course of study and experience

• Ability to apply baseline digital fluency and role‑appropriate AI literacy to use AI‑enabled tools responsibly and effectively for research, analysis, content creation, problem‑solving, operational tasks, and achieving business outcomes.

Marketing Executive (Engineering Industry)

Working Days: 5 days, Mon to Thurs 8:30am-6pm &  Fri 8:30am-5:30pm

Working Location: Commonwealth 

Salary: $2,900 ~ $3,500

We are looking for a Marketing Executive to develop B2B marketing strategies and campaigns locally and overseas.  You will be required to coordinate with staff in other departments and regional offices.

The goal is to ensure that the marketing efforts of the company add to the highest value to its business.

Responsibilities

• Develop efficient and intuitive marketing strategies and campaigns.
• Monitor corporate branding applications across all corporate and marketing materials to deliver quality corporate brand identity consistently.
• Organise and attend events such as seminars, trade shows, exhibitions and networking sessions.
• Conduct market research and analysis to assess current market trends, brand awareness and competitors.
• Managing the design, content and production of marketing collaterals, such as brochures, flyers and newsletters.
• Manage and update the content of the company’s website.
• Compiling and distributing product information to the sales department.
• Liaise and negotiate with vendors, suppliers, contractors and marketing agencies.
• Interact with country managers, sales team, principals and government agencies.

Requirements

• Diploma/Degree in Marketing, Communications or equivalent.
• At least 1-2 years of relevant work experience is preferred.
• Experience with Adobe Illustrator, WordPress and Google Analytics would be beneficial.
• Willing to travel for occasional business trips.

Kelly Chong Reg No:R26161160

The Supreme HR Advisory Pte Ltd EA No: 14C7279

Technical Sales Engineer (Outdoor)

• Working Days:  Monday to Friday
• Working Hour: 8am to 5.30pm
• Working Location: Ubi
• Salary: $ 4k to $6k (No Commission)

Requirements:

• At least 1 year or more experience in the electronics field preferably in components sale
• Familiar with Semiconductor design and application 
• Class 3 driving license
• IEEE graduates an advantage but diploma holders must have electronics background
• Must have good knowledge of local electronics business and be prepared to work hard meet the company’s goals and objectives
• Understand what is a Memory, Logic, MosFets etc.. (Will provide training if needed)
   

 Job Scope:

• Drive product line & develop strategies
• Create business opportunities with potential customers
• Conduct market survey
• Prospect for new accounts
• Service existing customers
• Provide market trend feedback
• Assist in price negotiations and customer delivery issues
• Knowledge of electronic component business
• Must be able to work independently with purchasing and design engineers
• Knowledge of semiconductors (Analog / Digital)
• Technical competency
• Flexibility to work long hours if needed to finish the daily assignments or to take on a new role if needed
  

Interested applicants kindly submit your resume through here or Whatsapp +65 9019 3218 (Joevy), and allow our Consultant to match you with our Clients. No Charges will be incurred by Candidates for any service rendered.

Tan Yu Jing Reg No: R26161199

The Supreme HR Advisory Pte Ltd EA No: 14C7279