Total 2,842 Senior Executive operations engineer job vacancies in Singapore

Your responsibilities include:

• Conceptualize M&E designs and execute the project with the detailed designs.
• Manage and engage client/consultant/ contractors and local authorities to drive project execution, submission to authorities and overall on-site construction supervision.

What you will need:

• A recognized university degree Mechanical or Electrical Engineering or Building Services.
• Minimum 4 years’ of relevant experience in design and implementation of building services.
• Strong team-working, communication and interpersonal skills. Able to build good working relationships with client and key stakeholders.
• Open to opportunities to be trained on a wide range of technical and management topics.
• Entry level will be considered for Engineer positions.

Engineering:

o The job holder will dedicate about one half of his/her time to Test development and characterization of Advanced devices for communication (either Optical or RF&mmwave)

o Within this scope, the job holder will also be in a position to promote his/her design background to bring improvements towards industrial Testability through DFT-like approach.

o Eventually the job holder will be involved in the Industrialization phase of the product they will be working on in development to discover the Industrial / Manufacturing completing their full view over Product Life cycle (from Design to Mass Production)

o In this Scope, the Job holder will be reporting to RFOC/Product Engineering/ASIA PAC Dev and Support Team.

RF Architecture and Design:

o The job holder will dedicate the other half of his / her time to RF design activities inside the RFOC organization. For this part of activity, the job holder will be under the supervision of RFOC/HWR&D/RF&mmWave competence centre.

o The responsibility will span from contributing to an advance RF communication standard developed with key industry partners, including Asian partners, to supporting two product families especially for the Asian market.

o The RF specialist will also contribute to the ST technical community in their area of expertise.

Key Responsibilities:

• Engineering responsibilities

o Contribute to Sicoya OAK (or similar) product development through Test Spec analysis, Product Test strategy optimization and then Test development, implementation and debug.

o Contribute to DFT approach analysis and propose optimization by leveraging his Design knowledge

o Acquire autonomy and test program development, debug and validation to support efficient industrial and optimized test solution

• RF design responsibilities:

o Contribute to NF60 standardization activities through architecture and design studies.

o Become a direct contributor to specific NF60 standard chapters, participate to NF60 committee regular reviews.

o Product support for ST60 product line and ST64 NBA frequency generator.

Requirements:

• Minimum education requirement PhD or post-doctorate in RF and analog design

• Minimum 5 to 10 years of experience in the silicon manufacturing industry

• Excellent knowledge of Bi-CMOS, CMOS and FD-SOI technologies

• Proven expertise in analog and digital design, RF and millimetre-Wave architecture and design

• Knowledgeable in DFT, test development and industrial testing

• Skilled in programming and simulation languages, including Python, Matlab and CAD development suites such as Cadence-Virtuoso

Key Responsibilities

Application Monitoring & Maintenance

Monitor application performance and availability.
Perform routine health checks, backups, and apply patches or upgrades.
Ensure compliance with security and operational standards.

Incident Management & Troubleshooting

Respond to and resolve application-related incidents promptly.
Diagnose root causes and implement corrective actions.
Escalate complex issues to development or infrastructure teams.

User Support & Training

Provide first-line support for application queries and issues.
Assist users with functionality and best practices.
Develop and maintain user guides and training materials.

Collaboration & Coordination

Work closely with developers to report bugs and suggest improvements.
Participate in testing new releases and deployments.
Coordinate with IT teams for integration and performance tuning.
Collaborate closely with manufacturing, engineering, and automation teams to identify and resolve system and process issues.

Documentation & Reporting

Maintain accurate records of incidents, changes, and resolutions.
Prepare regular reports on application performance and support metrics.
Document processes and ensuring knowledge base is up to date.

Others

Support business continuity and disaster recovery activities to ensure production resilience.
Ensure all application support activities comply with factory security, safety, and quality standards.
Proactively identify opportunities for process improvement, automation, and system optimization to enhance production efficiency.
Require on-call support during critical incidents. 

Required Skills & Qualifications

• Bachelor's degree in computer science, IT, or related field
• 3–5 years of relevant experience in application support
• Strong understanding of application architecture and databases
• Experience with troubleshooting tools and ticketing systems
• Basic programming/scripting skills (e.g., .NET, JavaScript, Python, C#, C++)
• Database Skills including Oracle, Postgres, BigData Solutions
• Agentic AI Basic Core Skills
• Excellent problem-solving and communication skills
• Willingness to work on-site and provide on-call support during critical incidents
• Knowledge of incident management and root cause analysis
• Experience with Rest API, Web backend, SQL and No-SQL databases
• Familiarity with DevOps tools and CI/CD pipelines
• Experience working with cross-functional teams (e.g., manufacturing, engineering)
• Ability to create user guides and training materials
• Experience in business continuity and disaster recovery planning
• Understanding of factory security, safety, and quality standards
• Knowledge of ITIL processes (Incident, Problem, Change Management)
• Familiarity with cloud platforms (AWS, Azure)
• Experience with monitoring tools (e.g., Zabbix)
• Understanding of information security best practices and compliance standards
• Experience in automation and process improvement initiatives

We regret to inform that only shortlisted candidates will be notified.

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PERSOL Singapore Pte Ltd • RCB No.200007268E • EA License No. 01C4394• Reg No: R1768000 (Nguyen Quynh Nhu)

Responsibilities

• Executive small-scale BAS projects including program & graphics design. 
• Analyse and resolve implementation issues to meet customer needs 
• Perform BAS preventive maintenance and verify M&V instruments
• Deliver quality work on time 
• Complete site interventions, repairs and commissioning as required 
• Provide technical support for warranty requirements 
• Build and maintain strong customer relationships
• Ensure efficient service to meet department goals
• Maintain test equipment properly
• Comply with all safety procedures

Requirements

• Degree/Diploma in Electrical/Building Automation Engineering
• At least 2 years experience in building automation systems 
• Strong technical problem-solving and solution recommendation skills 
• Familiar with networking, communication protocols, and IT infrastructure 
• Preferably experienced in BCA GM projects 
• Knowledge of HVAC, power meters and SCADA is an advantage 

At ENGIE, every talent has a role to play in accelerating the energy transition. Make a difference and enjoy a fulfilling professional experience. Take on exciting challenges and build a career path that reflects who you are.

Join us and be part of the adventure of the century!

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.

Role Summary

As a Senior Member of Technical Staff (SMTS), you are a module‑level CMP technical authority, responsible for defining CMP technical direction, leading FOAK developments, and driving cross‑functional execution across NAND nodes. As a SMTS (Senior Member of Technical Staff), you will be a part of revolutionary Next Generation NAND research & development CMP team driving Advanced NAND and CMP technology forward. The position promises ample opportunities for innovation, collaboration and testing a new dimension and scaling with Next Generation NAND. A SMTS CMP Engineer is a senior individual contributor responsible for defining, developing, and transferring advanced CMP processes for Micron NAND technologies. You will work directly with process integration and other process areas such as Wet Etch, CVD, Diffusion, Metals, Lithography & Dry Etch. You will work on state of the art and best in class CMP chambers & own the process roadmap to meet program and yield goals.

Main Responsibilities

• Own and lead key NAND CMP process modules, translating technology challenges into executable roadmaps across current and future nodes

• Drive cross‑functional execution across Technology Development, Process Integration, Manufacturing, and Equipment teams

• Lead FOAK CMP process development, including recipe architecture, control strategies, and integration alignment

• Ensure process robustness and manufacturability through run‑to‑run controls, SPC, qualification execution, and risk mitigation

• Resolve complex yield, defectivity, and integration issues using model‑based and data‑driven problem solving

• Define and execute process‑level hardware strategies in collaboration with equipment suppliers

• Act as a CMP technical leader, mentoring engineers, influencing adjacent process roadmaps, and communicating technology status and plans to senior stakeholders

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Other Responsibilities

• Mentor engineers through structured development; build SME pipelines; publish internal papers/BKMs and present to senior leadership; uphold Micron’s technical leadership expectations

• Integrates AI assisted tools and insights into daily work to improve efficiency, quality, or effectiveness, exercising sound judgment and complying with organizational standards and legal requirements.

• Contributes to a culture of continuous improvement by identifying, testing, and sharing AI enabled enhancements within one’s scope of work.

Candidate Profile

Minimum Qualifications / Experience

• PhD ≥12 yrs, or Master’s ≥15 yrs, of relevant experience in
  Electrical Engineering, Materials Science, Chemical Engineering, Physics, or related field,

• Experience in CMP Process Development

• Deep expertise in CMP chemistry, physics, and integration

• Publications/patents and strong record of technical contributions.

Must-Have Technical Skills

• In‑depth expertise in CMP fundamentals, including pad–slurry–wafer interactions, slurry chemistry at a mechanistic level, and pattern density/layout effects

• Strong understanding of multiple CMP process types (e.g., metal, dielectric, barrier/hardmask, poly‑Si/Si CMP)

• Extensive hands‑on experience with advanced 300 mm CMP OEM platforms, including driving hardware capability, throughput, and cost improvements

• Proven expertise in statistical process control (SPC), data analysis, and qualification methodologies

• Ability to independently drive complex technical execution, resolve yield and defectivity issues, and influence cross‑functional teams

Must-Have Soft Skills

• Demonstrated technical leadership in problem solving, with experience leading complex or multi‑disciplinary technical projects

• Strong ability to influence without authority across process integration, equipment, and manufacturing teams

• Clear and structured technical communication skills, including written documentation and stakeholder updates

• Strong analytical mindset with disciplined, data‑driven decision making

Embody Micron’s core values:

• People – Respect, develop and empower others

• Innovation – Drive continuous improvement and breakthrough thinking

• Tenacity – Show grit and determination

• Collaboration – Build trust and foster teamwork

• Customer Focus – Deliver excellence and value

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.
  

  Performs hardware, software, semiconductor design or telecomm engineering assignments. This job mapping should be used only if the position cannot be mapped specifically to other design/development engineering jobs.

Job requirement:

• Ability to perform first level investigation out of control situation and line excursions, abnormal lot/tool judgement due to inline OOC and OOS from SPC Chart.
• Process condition optimization.
• Work closely with equipment and production to ensure key module objectives are met.
• Evaluation to improve process margin.
• Cost reduction projects.
• Ensure safety, discipline and housekeeping compliance by all personnel.
• Analyze different types of defects and provide clear problem description with maintenance counterparts on troubleshooting.

Job requirement:

• Diploma in Electrical/Electronics/Chemistry/Microelectronics/Engineering or equivalent.
• Relevant working experience in Photo Process semiconductor front-end industry
• Willing to work in cleanroom environment.
• Able to perform 12-hour rotating shift
• An excellent team player with good interpersonal skill
• Strong logical thinking capability and good analytical skill
• Highly committed with good ownership and accountability
• Passion for the semiconductor / manufacturing industry
• Able to adapt in a fast pace environment and work under pressure
• Proficient in MS Office Applications

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.

ESSENTIAL DUTIES AND RESPONSIBILITIES 

In this position, you will work in the Material Engineering team within the Packaging R&D organization who owns and deploys best-in-class material engineering solutions to the top-edge product and technology development across advanced semiconductor packaging, flash memory product and host levels. Your essential duties and responsibilities include:

• Drive advancement in packaging materials by addressing material-related design and process challenges. Develop solutions to support next-generation package requirements, including smaller form factors, thinner die, higher interconnect density, increased power, and enhanced reliability.
• Lead the evaluation, development, and qualification of advanced packaging materials for both product development and high-volume manufacturing. Ensure compliance with industry standards and sustain high material quality to enable reliable, high-yield, and cost-efficient manufacturing.
• Responsible for material characterization, lab testing, and design of experiments (DOE) to simulate manufacturing processes and use-condition failure. Analyze thermal, mechanical, and environmental performance to ensure materials meet reliability and performance targets.
• This position will interface with package and product design (in particular, thermal and mechanical), reliability, failure analysis, assembly R&D, and process teams to define material requirements and solutions. Collaborate with suppliers to develop, optimize, and qualify materials for successful production integration.

Job Responsibilities

- Responsible for the design, development, testing, and maintenance of enterprise-level backend systems, reporting modules, and data platforms

- Perform system analysis, technical design, and feature implementation based on business requirements

- Responsible for Java backend service development and database business logic implementation

- Responsible for Oracle / OceanBase database development and optimization, including:

• Stored Procedures
• Packages
• Triggers
• Functions

- Optimize SQL queries and database performance to improve overall system stability and response efficiency

- Participate in RESTful API development and third-party system integration

- Use MongoDB, ClickHouse, and related technologies to support big data queries and analysis

- Responsible for system troubleshooting, performance tuning, and production environment support

- Configure, build, and test system-related technical components

- Collaborate with product, frontend, and other technical teams to ensure smooth project delivery

- Participate in relevant technical research and system optimization work according to project needs

Job Requirements

Technical Skills

- Proficient in Java SE / Java EE and object-oriented programming (OOP)

- Familiar with enterprise-level development using Spring Boot / Spring Framework

- Familiar with MVC architecture design

- Experience with MyBatis / iBatis development

- Solid experience in SQL performance optimization

- Proficient in Oracle database optimization and stored procedure development

- Experience in multithreaded development and system performance tuning

- Familiar with RESTful API design and system integration patterns

- Familiar with version control tools such as SVN / Git

- Experience with MongoDB, ClickHouse, or big data platforms is preferred

- Familiarity with Linux environment operations and deployment is preferred

- Familiarity with AI-assisted development tools such as Cursor, Claude Code, GitHub Copilot, etc. is preferred

- Experience developing systems for finance, government, or large enterprises

- Experience with microservices architecture development

- Experience with Docker, CI/CD, or cloud deployment

- Experience with high-performance data processing or real-time data analysis

- Experience in system architecture design is preferred

- Experience leading development teams or projects is a plus

Personal Attributes

- Good analytical and problem-solving skills

- Careful and detail-oriented, with a strong focus on code quality and system stability

- Able to handle high-concurrency and large-scale data scenarios

- Good teamwork and communication skills

- Proactive, responsible, and highly accountable

Qualifications

- Bachelor’s degree or above in Computer Science, Software Engineering, Information Technology, or a related field

- At least 4–5 years of Java backend development experience

- Experience developing large-scale enterprise systems or high-concurrency systems is preferred

Language Requirements

- Good English communication skills

- Fluency in spoken and written Chinese is essential, as the role requires frequent liaison with Chinese-speaking counterparts and stakeholders, and the preparation, review and handling of Chinese-language work materials.


岗位职责

- 负责企业级后台系统、报表模块及数据平台的设计、开发、测试与维护

- 根据业务需求进行系统分析、技术设计及功能实现

- 负责 Java 后端服务开发及数据库业务逻辑实现

- 负责 Oracle / OceanBase 数据库开发与优化，包括:

• Stored Procedure
• Package
• Trigger
• Function

- 优化 SQL 查询及数据库性能，提升系统整体稳定性与响应效率

- 参与 RESTful API 开发及第三方系统整合

- 使用 MongoDB、ClickHouse 及相关技术支持大数据查询与分析

- 负责系统问题排查、性能调优及生产环境支持

- 配置、构建及测试系统相关技术组件

- 与产品、前端及其他技术团队协作，确保项目顺利交付

- 根据项目需求参与相关技术研究与系统优化工作

职位要求:

技术能力

- 精通 Java SE / Java EE 及面向对象编程（OOP）

- 熟悉 Spring Boot / Spring Framework 企业级开发

- 熟悉 MVC 架构设计

- 具备 MyBatis / iBatis 开发经验

- 扎实的 SQL 性能优化经验

- 精通 Oracle 数据库优化及存储过程开发

- 具备多线程开发及系统性能调优经验

- 熟悉 RESTful API 设计与系统整合模式

- 熟悉 SVN / Git 等版本控制工具

- 有 MongoDB、ClickHouse 或大数据平台经验者优先

- 熟悉 Linux 环境操作及部署者优先

- 熟悉 AI 辅助开发工具（如 Cursor、Claude Code、GitHub Copilot 等）者优先

加分项

- 有金融、政府或大型企业系统开发经验

- 有微服务架构（Microservices）开发经验

- 有 Docker、CI/CD 或云端部署经验

- 有高性能数据处理或实时数据分析经验

- 有系统架构设计经验者优先

- 有带领开发团队或项目经验者更佳

个人能力

- 具备良好的分析与问题解决能力

- 工作认真细致，注重代码质量与系统稳定性

- 能够处理高并发及大规模数据场景

- 具备良好的团队合作与沟通能力

- 工作积极主动，责任感强

任职资格

- 计算机科学、软件工程、信息技术或相关专业本科及以上学历

- 至少 4–5 年 Java 后端开发经验

- 具备大型企业系统或高并发系统开发经验者优先

语言要求

- 具备良好的英语沟通能力

- 能使用普通话沟通者优先，以便与华语客户及合作伙伴进行日常交流


Lumina Advisory & Global Search Pte Ltd | 25C3262

Joyce Yeo | R1218489

THE ROLE: 

As a Senior Engineer, you will collaborate with various Product Development Groups. This individual serves as a critical technical point of contact to the business, design, platform validation and product engineering teams. We have competitive benefit packages and an award-winning culture. Join us!  

THE PERSON: 

A successful candidate is one who can drive technical decisions independently, has accountability for accuracy, reliability and completeness of assignment results critical to the project’s success. This role allows the opportunity to influence technical decisions that have a significant impact on multiple products or the product line.  

KEY RESPONSIBILITIES: 

• Ensures high uptime, ensures preventive maintenance (PM) execution, and seamless vendor coordination for resolving tools hardware and software issues. Primary advanced toolset coverage: Focused Ion Beam, Reactive Ion etchers, Nano‑probers, Scanning electron microscopes and Transmission electron microscopes 
• The role partners closely with equipment owners, lab operations, EHS, and external OEMs to sustain capability, drive MTBF/MTTR improvements, and enable rapid turns on high‑priority cases.
• Design new lab space with strict environmental control involving vibration, EMI and acoustics.
• Lead structured troubleshooting and root‑cause eradication (5‑Why, Ishikawa, FMEA); convert escapes into standard work and documented fixes
• Serve as single point of contact for OEMs and third‑party service providers; coordinate field service, escalations, and remote diagnostics
• Manage service contracts, PM bundles, and time‑and‑materials events; negotiate scope vs. cost; track vendor KPI adherence and corrective actions
• Enforce LOTO, ESD, chemical/gas handling, UHV safety, and radiation/beam compliance as applicable
• Partner with FA engineers on readiness gates for new methods/fixtures; support tool installation, lab moves, and capability upgrades
• Provide on‑call/shift coverage as needed for bring‑up, critical debug, and factory‑stop events

PREFERRED EXPERIENCE: 

• Hands on maintenance experience with complex capital equipment involving vacuum systems, motion/servo control, pneumatics, high voltage, and embedded SW/FW
• Demonstrated ability in systematic troubleshooting, reading electrical/pneumatic schematics, and using diagnostic tools (oscilloscope, DMM, leak detector, RGA)
• Effective communication with vendors and cross site teams; ability to coordinate multi party interventions under time pressure
• Experience in failure analysis tools, including alignments, stage/probe calibration, column health, and detector
• Knowledge of UHV, turbo/cryogenic pumps, gas handling, plasma sources, beam columns, and vibration/thermal isolation
• Lab‑based role with occasional off‑shift or weekend coverage during critical events and planned PMs
• Some travel for OEM training, factory repair, or acceptance tests may be required

ACADEMIC CREDENTIALS: 

• Bachelor’s degree in Mechatronics Engineering (or Mechanical/Electrical with mechatronics focus)

About the Role

The primary responsibility of the E & I Senior Plant Engineer is to ensure the new equipment installation and process modifications to be carried out per requirements. They are also responsible to uphold equipment application safety standards and ensure regulatory compliance. By developing and implementing safety protocols, conduct regular audits and inspections, and train personnel on equipment maintenance and service safety practices.

Key Responsibilities

PLC program modification, take charge new equipment installations, process modifications, supporting equipment  PM and trouble shooting

• PLC program modification and trouble shooting
• New equipment specification confirmation, purchasing, installation and commissioning
• Carry out modification
• Conduct design review
• Equipment trouble shooting
• Equipment trouble root cause analysis

Training for Engineers

• Provide training for engineers

Responsible for workplace safety and health activities in Process development section programs.

• Planning for yearly SDM
• Implement section program to achieve related KPIs

Lead and manage ECR reduction and closure

• Investigate cause and execute solutions on time

Ensure all projects are delivered on time, within budget and meet the desired specifications

• Review all vendor contracts and recommend the performance of contractors.
• Conduct vendor service performance audit.
• Liaise with HQ technical team for process improvement and equipment issues

What We’re Looking For

• Bachelor-Degree in Electrical Engineering or equivalent (min 5 years relevant working experience)
• Master-Degree in Electrical Engineering or equivalent (min 3 years relevant working experience)
• Possess High pressure equipment related cert (advantage)
• Strong PLC & other electrical problem-solving and analytical skills
• Good communication and negotiation skills
• Riche experience in different kinds of motorized equipment service, troubleshooting
• Intermediate MS Office
• Good Written and spoken English.
• Good presentation skills to share and brief co-workers and management with clarity.
• Good knowledge in Mechanical related, e.g. material, application and etc.
• Able to read P&ID drawings.
• Able to carry out hands-on work.
• Have leadership and supervision skills to guide and coach team members
• Independent individual that does not require supervision. 
• A good team player who can collaborate across different teams and departments.
• Positive working attitude
• Willing to learn new things.
• Self-motivated to look for problems and solutions.
• Inquisitive and innovative mind to explore new areas and technologies.
• Possessa safety mindset

Others:

• Location: Jurong Island (Company Transport provided)
• Commence work: ASAP.
• Applicants can work in Singapore without requiring a work pass.
• Working Hours: Mon ~ Fri from 8:00 am - 4:45 pm

Why Join Us?

• Join a reputable MNC with structured learning and growth opportunities.
• Attractive compensation with performance bonuses, AWS, allowances and comprehensive employee benefits.
• Supportive and collaborative team culture
• Company-provided transport to Jurong Island

Job Overview

We are seeking an experienced Senior C# Software Engineer to design, develop, and support enterprise applications built on the .NET platform. This role requires a strong technical contributor who is highly familiar with the systems and solutions they support, and who can take ownership of application functionality, performance, and stability.

The ideal candidate demonstrates strong technical awareness of current responsibilities, understands the architecture of the products they work on, and can diagnose and resolve complex system issues.

Key Responsibilities

Application Development

• Design, develop, and maintain backend applications using C# and the .NET framework
• Build scalable and maintainable software solutions following industry best practices
• Write clean, efficient, and well-documented code

System Support & Ownership

• Maintain strong familiarity with the products and systems supported
• Investigate and resolve application issues through structured troubleshooting and root cause analysis
• Ensure system stability, performance, and reliability in production environments

Solution Design

• Participate in system design discussions and propose technical improvements
• Contribute to application architecture, system integration, and performance optimization
• Collaborate with cross-functional teams to ensure technical solutions align with business requirements

Testing & Quality Assurance

• Develop and execute unit tests and integration tests
• Support system integration testing and deployment activities
• Ensure high code quality through code reviews and best practices

Documentation & Knowledge Sharing

• Maintain technical documentation for systems and applications
• Share knowledge with team members and contribute to technical discussions
• Provide guidance to junior developers where required

Requirements

• Bachelor’s Degree in Computer Science, Software Engineering, or related discipline
• Minimum 5–7 years of experience in C# / .NET development
• Strong hands-on experience with C#, .NET, and object-oriented programming
• Solid understanding of software architecture and system design
• Experience developing and maintaining enterprise applications
• Ability to troubleshoot complex application issues and perform root cause analysis
• Strong understanding of REST APIs, application integration, and backend services
• Familiarity with SQL databases and data access technologies
• Strong analytical thinking and problem-solving capability
• Excellent communication skills and ability to collaborate with cross-functional teams

Preferred Experience

• Experience with modern .NET frameworks (.NET Core / .NET 6+)
• Familiarity with microservices architecture
• Exposure to cloud platforms or containerized environments
• Experience with CI/CD pipelines and DevOps practices

Please send your detailed resume in MS Word format to resume@goldtecHRs.com with

• Education Level
• Working experiences
• Each employment background
• Reason for leaving each employment
• Last drawn salary
• Expected salary
• Date of availability

Job Description & Requirements

We are seeking a talented Senior Navigation and Control Engineer to drive the development of advanced behavior, planning, and control strategies for our global fleet of autonomous cleaning robots. This role is ideal for an engineer passionate about robotics, algorithm development, and system integration. You will work on planning, real-time decision making and implement features such as multi-floor navigation and docking control systems. You will also work with other engineers to develop robust testing pipelines, aimed at ensuring quality and reliability of our robots.

You will own independent deliverables, collaborate closely with SLAM and Perception engineers, and play a critical role in shaping the next generation of autonomous systems. Key responsibilities include:

Key Responsibilities

• Design and implement modular behavior tree architectures for complex and robust robot decision-making.

• Develop and optimize global planning algorithms (A*, D*, RRT*, PRM, etc.) for dynamic environments.

• Design and tune local planners and controllers for smooth and safe robot motion (e.g. MPC, TEB, DWA)

• Optimize planning and control systems to ensure real-time system performance, including timing guarantees for control loops.

• Collaborate with SLAM and Perception engineers to align navigation with perception, mapping.

• Develop comprehensive test cases for validating algorithms and software in both simulated and real-world environments, to ensure reliable performance.

• Maintain comprehensive documentation of all code implementations and test cases

• Explore advanced planning and control methods for real-world deployment (e.g., reinforcement learning-based planning)

Qualifications & Experience

• Bachelor’s or Master’s degree in CS, Robotics, or a related field (or PhD with relevant focus)

• 3+ years of industry experience in developing and deploying behavior, planning and control systems for autonomous robots.

• Proficient in C++ and Python development on Linux.

• Experience working with ROS1 / ROS2.

• Solid foundation in data structures, algorithms, kinematics, dynamics, and control theory

• Strong understanding of robot dynamics, kinematics, and control theory.

• Hands-on experience with behavior planning frameworks (e.g. BehaviorTree.CPP).

• Strong understanding of global and local path planning algorithms.

• Familiarity with sensor modalities (e.g. LiDAR, RGBD cameras, IMUs)

• Strong attention to detail, with excellent problem-solving and debugging skills

• Experience with reinforcement learning applied to behavior, planning or control is a bonus.

• Experience with optimizing software for embedded hardware (e.g., Jetson, ARM) is a bonus.

If you have a passion for driving meaningful operational improvements, excel at analytical problem-solving, and thrive in a dynamic scaleup atmosphere, we invite you to join LionsBot and help shape the future of robotics innovation.