Total 17 job vacancies by Advanced Micro Devices (singapore) Pte Ltd

THE ROLE:

We are looking for an experienced Verification Engineer to join our team for cutting-edge server memory products. This individual will be responsible for driving the verification efforts of DDR interfaces, including advanced memory protocols such as DFI, DDR5, and LPDDR5/LPDDR6, across a range of DIMMs (Dual In-line Memory Modules). The ideal candidate will possess advanced knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python/Perl.

THE PERSON:

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc.  You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:

• Work with a team verification engineers in the development and execution of verification plan for DDR5, LPDDR5, and DFI memory systems in server products.
• Comprehend the PHY's interaction in the complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features of the memory interface.
• Understand RTL and micro-architecture sufficiently to engage in cross functional discussions with IP/Domain architects and Design engineers for planning and debug.
• Knowledge sharing and other contributions to verification methodology
• Support Post-Si teams for Product Performance, Power and functional issues debug/resolution 

PREFERRED EXPERIENCE:

• Developed and implemented SystemVerilog and UVM (Universal Verification Methodology) based testbenches, simulation environments, and functional coverage models for DDR5 and LPDDR5 systems.
• Worked closely with hardware, firmware, and software teams to align on system-level memory architecture, identify potential integration issues, and define validation requirements early in the design phase.
• Built VIPs and BFMs for memory interfaces from scratch (preferrable)
• GLS, NLP, XPROP simulation experience is preferable
• Strong proficiency in system verilog assertions, constraints and coverage.
• Worked in formal verification methods, with proven record of tool usage beyond the standard apps.
• Excellent communication, management, and presentation skills. 

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in related discipline

THE ROLE:

We are seeking a Staff Packaging Engineer to lead advanced package industrialization from NPI through HVM, driving DFM integration and manufacturing readiness with OSAT partners in multiple countries to ensure stable ramp, yield, quality, and delivery performance.

THE PERSON:

Based in Singapore, you will work closely with OSAT operations and engineering teams across multiple countries, partnering daily with manufacturing engineering, quality, and operations to establish/maintain POR, close manufacturing gaps, and rapidly resolve factory issues across advanced packaging technologies (e.g., 2.5D interposer and fan-out).

Collaborate cross-functionally (design, substrate, reliability, test, quality, supply chain, and program management) and apply structured methodologies (DFM/DOE/SPC/FMEA/8D) to drive risk reduction and ramp readiness.

This is an execution-driven role requiring strong advanced packaging process expertise, manufacturing / operations acumen, and the ability to influence across global teams and external partners to deliver robust, scalable production.

KEY RESPONSIBILITIES:

NPI to HVM Industrialization

• Lead end-to-end industrialization of advanced package technologies from NPI through HVM readiness across external assembly/test manufacturing partners and foundry partners.
• Own NPI-to-HVM execution: lead readiness reviews, drive risk mitigation, and govern ramp activities; collaborate closely with OSAT engineering teams on process development, qualification, and optimization to ensure robust, scalable, and manufacturable assembly and test solutions across sites.

Design for Manufacturing (DFM) Integration

• Primary interface between package design/technology development and external manufacturing partners to ensure manufacturable architecture and clear DFM requirements.
• Identify/close manufacturability gaps early; drive technology-to-manufacturing transfer and best-practice deployment.

External Supplier Manufacturing Management

• Partner with outsourced manufacturing sites to ensure manufacturing capability, capacity readiness, and process maturity for advanced packaging platforms.
• Drive yield, cycle time, quality, and delivery performance; lead defect reduction and yield improvement with site teams.
• Provide hands-on execution leadership OSATs: lead daily/weekly manufacturing reviews, expedite issue triage with site teams, and align action owners across manufacturing, quality, and supply chain to protect ramp and delivery.
• Manage out-of-control lot disposition; implement CAPA and share BKM.
• Lead technical reviews, audits, ramp readiness assessments, and coordinated change management with internal/external stakeholders.

Yield, Quality, and Process Control

• Drive process control and continuous improvement using DOE/SPC/FMEA and data-driven root cause analysis.
• Lead cross-functional investigations for yield excursions, reliability risks, and field quality issues, ensuring timely containment and corrective actions (8D).
• Develop monitoring/early-detection mechanisms and ensure alignment to quality, reliability, and qualification requirements.

Cross-Functional Program Execution

• Partner cross-functionally (design, tech dev, reliability, product/test, quality, supply chain, program management) to align deliverables and execute to plan.
• Drive readiness reviews and risk assessments; track actions and communicate clear status/escalations to stakeholders.
• Support program teams in achieving cost, schedule, capacity, and production targets for Enterprise, Client, and AI accelerator products.

PREFERRED EXPERIENCE:

• Experience in semiconductor packaging/assembly manufacturing or product engineering, with strong on-site execution in high-volume environments.
• Proven NPI and ramp leadership, including supplier management, process qualification, manufacturing readiness, and yield ramp monitoring.
• Demonstrated ability to work effectively with OSAT manufacturing operations in multiple countries, including structured communication, escalation management, and fast-turn coordination across site teams and global stakeholders.
• Demonstrated success in yield improvement/defect reduction, root-cause closure, and disciplined change management in HVM.
• Hands-on advanced packaging experience (e.g., 2.5D interposer, fan-out, 3D, high-density flip-chip; plus RDL/TCB/hybrid bonding familiarity) with OSAT/factory interface experience.
• Strong problem-solving and analytics using structured methods (DOE/SPC/FMEA/8D) and manufacturing data to drive decisions.
• Strong stakeholder management across cross-functional teams and external partners; able to translate issues into clear action plans and drive closure.
• Professional fluency in English, Mandarin, and Korean to support technical documentation, stakeholder communication, and cross‑site engineering collaboration across APAC.

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in Mechanical Engineering, Materials Science, Electrical Engineering, Chemical Engineering, or a related engineering discipline.

THE ROLE: 

We are looking for an adaptive, self-motivative Design Verification (DV) engineer to join our growing PLL team. As a key contributor, you will be part of a leading team that drives and improves AMD's ability to deliver the highest quality, industry-leading technologies to the market. The Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. 

THE PERSON:

• Excellent analytical and critical thinking skills along with attention to details
• Must be an initiative-taker, able to drive tasks independently and efficiently to completion
• Strong/effective communication skills
• Enthusiastic team-first mentality
• Ability to provide mentorship and guidance to junior engineers

KEY RESPONSIBILITIES:

• Analyze complex verification and digital design problems and propose verification / micro-architecture solutions

• Develop RTL and Firmware validation.

• Drive/develop ASIC verification flows and scripts.

• Create Verification architecture.

• Work with the RTL Design team to ensure functional correctness and coverage.
• Support silicon bring-up and diagnostics.

• Support Post-silicon debug, root cause bug, provide solution or workaround.

PREFERRED EXPERIENCE:

• Proven experience in design verification from specification to successful silicon.
• Experience in PLL, high-speed interfaces such as DDR, PCIe and high-speed SERDES.
• Experience in designs with multiple power domains.
• Experience in designs with multiple clock domains.
• Experience in behavior modeling for Analog Circuits.
• Experience in industry-standard ASIC CAD tools for verification, simulation, synthesis, STA, CDC, UPF, power estimation, etc
• Progressive experience in RTL Design

ACADEMIC CREDENTIALS:

• Bachelors or Masters Degree in Computer Engineering/Electrical Engineering 

THE ROLE:

This role is responsible for end‑to‑end ATE test solution architecture and execution for next‑generation AMD products. This role owns technical leadership across pre‑silicon planning and post‑silicon execution, ensuring that ATE test solutions meet AMD’s quality, performance, cost, and reliability objectives while enabling fast time‑to‑market.

This position partners closely with Design, Product Engineering, Platform Engineering, Device Analysis, Foundry, Quality & Reliability, Manufacturing, and OSAT teams to define and deliver robust, scalable ATE strategies across wafer sort and final test. The role acts as a technical authority and lead engineer, guiding teams through complex test challenges and driving innovation in test methodologies and manufacturing processes.

THE PERSON:

This is a senior individual contributor leadership role for a highly experienced test engineer with deep hands‑on ATE expertise and strong technical influence. The ideal candidate brings a proven track record of owning ATE test solutions across multiple product cycles, making critical technical decisions, and influencing cross‑functional stakeholders without formal people‑management responsibility.

The candidate is expected to operate as a subject‑matter expert and technical leader, setting direction, mentoring senior engineers, and shaping best practices across ATE domains. This role requires a strategic mindset, strong execution discipline, and the ability to balance test coverage, yield, cost, and schedule trade‑offs in high‑stakes product environments.

KEY RESPONSIBILITIES:

Technical Leadership & Ownership

• Own pre‑silicon ATE planning and post‑silicon execution for assigned product groups, from early architecture through HVM ramp.
• Define and drive ATE test strategies and architectures aligned with product roadmaps and business priorities.
• Serve as the technical authority for ATE readiness at all NPI milestones, including first silicon, bring‑up, characterization, qualification, and high‑volume manufacturing.
• Lead design collaboration to achieve First Time Right (FTR) ATE test patterns in a disciplined, time‑bound manner.

Product Engineering & Execution

• Define and execute product engineering test strategies that enable robust validation, characterization, and manufacturability.
• Drive yield improvement, test time reduction, and cost optimization through test program architecture, pattern optimization, and data‑driven analysis.
• Support multiple product families concurrently by promoting reuse, common platforms, and scalable methodologies.
• Troubleshoot and resolve complex test, silicon, and manufacturing issues across wafer sort and final test.

Cross‑Functional Collaboration

• Partner closely with Design, Verification, Test, Product Engineering, Software, Manufacturing, and Operations teams to ensure test solutions meet quality, reliability, and cost targets.
• Work directly with OSAT partners and internal factories to ensure consistent, high‑quality production execution.
• Act as a key technical interface across global teams, influencing decisions through data, expertise, and credibility.

Innovation, Data & Advanced Methodologies

• Drive the adoption of advanced data analytics, AI, and ML techniques to improve test efficiency, yield learning, and decision‑making.
• Champion continuous improvement through new processes, tools, automation, and state‑of‑the‑art ATE methodologies.
• Establish best practices and technical guidelines that improve productivity and scalability across ATE teams.

Mentorship & Technical Influence

• Mentor senior and staff‑level engineers, providing technical guidance and design reviews.
• Contribute to capability development, technical roadmaps, and succession planning in partnership with management.
• Influence technical direction across teams without direct people management responsibility.

Quality & Compliance

• Ensure compliance with internal processes, manufacturing standards, and ISO requirements.
• Maintain high quality of deliverables and disciplined execution across all phases of product development.

PREFERRED EXPERIENCE:

• Experience in the semiconductor industry with deep specialization in ATE test engineering
• Strong hands‑on expertise in: ATE test methodologies, DFT and testability concepts, Product characterization, qualification, and manufacturing test
• Proven track record of owning ATE test solutions across multiple full product cycles (pre‑silicon to HVM)
• Experience working with outsourced test (OSAT) models and high‑volume manufacturing environments
• Strong background and demonstrated results using data analytics, AI, or ML in test or manufacturing contexts
• Ability to drive complex technical decisions across cross‑functional teams
• Exceptional analytical, problem‑solving, and troubleshooting skills
• Strong communication and influencing skills in multi‑site, multicultural environments
• Demonstrated openness to innovation and continuous improvement

ACADEMIC CREDENTIALS:

• Bachelor/Master in Electrical/Electronic Engineering

THE ROLE:

The Technical Lead is responsible for the test solution for a next-generation AMD Products. This position serves as the Test Engineering team's Technical Leader and go-to expert for solutions.  This position requires engagement with Product, Design, Platform Engineering, Device Analysis, Foundry, Quality and Reliability Engineering to drive test and characterization plan, 1st silicon bring-up, silicon debug, attainment and optimization of yield and performance distributions, test costs and product quality for next-generation AMD products.

This role offers opportunities for experienced Engineers who are interested in growing their technical scope over time, based on individual performance and business needs.

THE PERSON:

We are looking for one with a passion for technical development, possessing broad technical leadership, critical problem solving and troubleshooting skills. The person must be a team player and have good and effective communications to deep dive into technical discussion with other members across the globe and use data to illustrate their points. This person is expected to be independent, self-starter, well organized and have the sense of responsibility to see projects through beginning to the end as well as the ability to lead by influence. This person is expected to be market savvy and comfortable in a multi-tasking environment.

KEY RESPONSIBILITIES:

New Product Introduction (NPI)

• Define and drive pre silicon test and characterization strategies for complex SoC products.
• Establish DFT and pattern requirements, and work with Design and Verification teams to ensure test readiness prior to first silicon.
• Lead first silicon bring up, silicon debug, and characterization execution across PVT corners.
• Analyze yield, performance distributions, and device failures; lead root cause analysis and drive corrective actions across global teams.
• Perform circuit sensitivity analysis, interpret findings, and guide deep dive investigations to resolution.
• Drive innovation in SoC test, debug, DFT, and test methodology, translating ideas into production ready solutions.

Production & Cost Optimization

• Own test content optimization to meet product quality and cost targets.
• Drive yield, test time, and margin improvements from wafer sort through backend test.
• Partner with manufacturing and quality teams to ensure stable, scalable production.

PREFERRED EXPERIENCE:

Technical

• Strong hands-on experience supporting complex SoC products (e.g., mobile or automotive processing units).
• Proven technical leadership across at least one full SoC product lifecycle (pre silicon to production).
• Deep expertise in DFT and ATE test methodologies, spanning areas like ATPG Scan, MBIST, Functional, and High‑Speed IO testing across complex SoC environments.
• Strong experience with Advantest 93k/Teradyne test platforms.
• Solid understanding of CPU / GPU / SoC architectures with system level interactions as a plus.
• Strong programming or scripting skills (Python, C/C++, Perl, Java).
• Experience with industry EDA tools (Mentor, Synopsys, Cadence) is a plus.

Leadership

• Demonstrated ability to act as a technical decision‑maker and mentor within the test organization.
• Strong communication skills to engage deeply with global, cross‑functional engineering teams.
• Willingness and capability to take on broader ownership, including mentoring engineers and contributing to long‑term test strategy and team development.
• Strong ability to lead by influence
• Ability to program manage and drive test schedules and deliverables

ACADEMIC CREDENTIALS:

• Bachelor/Master in Electrical/Electronic Engineering

THE ROLE:

We are the New Product Introduction (NPI) test engineering team defining and providing test solutions for AMD’s High Performance Compute products in a fast-paced environment under the Product Engineering Organization.

If you are looking for a fulfilling and challenging career as an high end leader leading NPI System Level Test (SLT) Product Development, you are at the right place! As a Senior Manager in SLT Product Development Engineering, you will be responsible for growth and develop high performance SLT team to drive SLT solutions to address upcoming technology development, NPI business milestones and KPI (test time, yield, cost, quality). The expectation is to be in a position of leadership, collaborating with architecture and design teams, Product & Test Engineering teams, Customer Quality teams, software & platform teams to come up with the best solution that balances quality and cost. You will experience working with and learning from AMD’s talented engineering teams around the world

THE PERSON:

We are looking for someone with strong technical, analytical, leadership and problem-solving skills, as well as demonstrating the characteristics of an independent and resourceful individual.

The applicant must have a proficient understanding of x86 CPU and GPU architecture and functionality, as well as a broad understanding of various industry standard bus protocols, such as DDR, PCIe, and USB.

KEY RESPONSIBILITIES:

• Accountable to drive and develop SLT solutions to meet business milestones, cost and quality in system level scope.
• Solves complex, novel, and non-recurring problems; initiate significant changes to existing processes/methods and leads development and implementation
• Conduct engineering evaluations and analysis to drive closure of production issues
• Develop and architect SLT logging or data collection flow in manufacturing
• Influences technical decisions that have a significant impact on final product
• Involves collaboration on or assuming the consultative or leadership responsibilities for a specific project or for product development initiatives
• May provide technical supervision or mentoring junior engineers
• Upscale overall team capabilities on low level system debug for AMD data center product families

PREFERRED EXPERIENCE:

• Knowledge or working experience on GPU architecture, X86 architecture, SoC design and power management features
• Experience with SOC (System-On-Chip), Firmware and Software interaction
• Software programming and scripting proficiency (Java, Shell script, Perl, Ruby, Python)
• Proficiency in Windows and Linux operating systems
• Experience with HBM (High Bandwidth Memory) and/or HSIO (High Speed Input Output) and/or Co-Packaged Optics is a strong plus
• Experience with HVM (High Volume Manufacturing) is a strong plus
• Strong and effective presentation, written and verbal communication skills, and the ability to work with geographically distributed product engineering teams
• Excellent interpersonal, organizational, and analytical skills

ACADEMIC CREDENTIALS:

• Bachelor/Master in Electrical Engineering, Computer Engineering, or comparable disciplines

THE ROLE:

The Product Yield Engineering team seeks an experienced engineer to support the development and launch of high-quality AI, Graphics, CPU, APU, and custom design products. The primary objective is to optimize manufacturing costs and ensure timely market delivery. This role requires cross-functional collaboration with engineering, design, foundry, and data teams to resolve complex challenges, accelerate product ramp-up, and drive ongoing yield improvements.

THE PERSON:

• Strong AI-forward data science skills with experience in big data models, databases, and machine learning
• Direct experience in JMP or equivalent data analysis tools.
• Strong scripting capability including using AI to extract and automate complex data analysis
• An advanced degree in a related field may reduce the minimum experience requirement

KEY RESPONSIBILITIES:

• Manage product wafer costs, including yield and test content, to meet quality and yield targets
• Analyze yield metrics to forecast supply and product performance
• Implement best practices for test and characterization
• Use diagnostics and failure analysis to reduce defects in foundry environments
• Collaborate with internal and external foundry teams to identify and implement process improvements
• Engage with engineering and business units to define and achieve program requirements for defectivity, power, performance, reliability, and quality

PREFERRED EXPERIENCES:

• Experience in process technology or product development, preferably with leading-edge foundries, assembly, and test operations.
• Understanding of functional and design-for-test methodologies, structures, and practices
• Technical expertise in the productization of new and advanced technologies
• Knowledge of leading edge (FinFET, GAA, etc.) semiconductor device physics
• Semiconductor manufacturing experience

ACADEMIC CREDENTIALS:

• Bachelor's degree in electrical engineering, Computer Engineering, or Computer Science or a related degree in Math, Sciences, or Statistics

THE ROLE:

We are the high-end test engineering team providing test solutions for Data Center New Product Introduction (NPI) under the Product Engineering Organization. We do exciting product development for leading-edge technology that will power the next generation processors used for high performance computing, data centers, and enterprise servers.

If you are looking for a fulfilling and challenging career as an engineer leading SLT (System Level Test) IVR (Integrated Voltage Regulator) Engineer, you are at the right place! In this role, you will be responsible for defining, driving and enabling SLT test solution with on-chip integrated voltage regulator to meet NPI business milestones and KPI (test time, yield, cost, quality). The expectation is to perform leadership to interact with Silicon/Board/Power design teams, Product & Test Engineering teams, Customer Quality teams, software & platform teams to bring new product from first silicon to HVM (High Volume Manufacturing) with aggressive schedule. You will experience working with and learning from AMD’s talented engineering teams around the world.

THE PERSON:

We are looking for someone with strong technical, analytical, leadership and problem-solving skills, as well as demonstrating the characteristic of an independent and resourceful individual. The applicant must have a proficient understanding of High Power Delivery (above 1kW) design, power capacitors and inductors, buck/boost converters, and ideally has experience with IVR (Integrated Voltage Regulator) as well as a broad understanding of silicon VFT (Voltage/Frequency/Temperature) behavior, on-die silicon power integrity, and system level power management etc.

KEY RESPONSIBILITIES:

• Accountable to provide leadership to meet business milestone, cost and quality in GPU system level test area.
• Collaborate with internal teams to drive IVR (Integrated Voltage Regulator) SLT swim lane from pre-silicon, ASIC initial bring up to HVM (High Volume Manufacturing)
• Solves complex, novel, and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation
• Conduct engineering evaluations and analysis to qualify cutting-edge IVR for HVM and drive closure of GPU production issues
• Profile or characterize PI (Power Integrity), voltage droop, or power delivery issue observed on SLT platforms in collaboration with board/silicon designers
• Involves collaboration on or assuming the consultative or leadership responsibilities for a specific project or for product development initiatives
• May provide technical supervision or mentoring junior engineers
• Upscale overall team capabilities on low level system debug for AMD data center product families

PREFERRED EXPERIENCE:

• Experience and with good understanding of Power Delivery design for high power GPU product (above 1kW), and knowledge in state-of-the-art of IVR (Integrated Voltage Regulator)
• Strong expertise with using analyzers and oscilloscopes, and other debug tools
• Knowledge and working experience on GPU and HBM architecture, SoC design and SoC power management features are a strong plus
• Strong and effective presentation, written and verbal communication skills, and the ability to work with geographically distributed product engineering teams
• Proficiency in Windows, and Linux operating systems
• Basic scripting proficiency for automation (Shell script, Perl, Ruby, Python)
• 8 years or more industry experience

ACADEMIC CREDENTIALS:

• BS/MS Electrical Engineering, Computer Engineering, or comparable disciplines

LOCATION:

Singapore

THE ROLE: 

In this role, you will work closely with other firmware engineers, developers and architects across various IPs in designing and implementing firmware that spans pre-silicon and post-silicon for all AMD SoCs.  

THE PERSON: 

You are passionate about firmware development with creative and effective problem-solving skills, a motivated, self-starter who can work both independently and collaboratively in fast paced environments. You have excellent technical communication, interpersonal and leadership skills. 

KEY RESPONSIBILITIES: 

• Design, develop, debug, verify and/or validate firmware, software and/or hardware 
• Participant in day-to-day firmware development work  
• Provide consultation to internal and external customers regarding AMD features and programming requirements 

PREFERRED EXPERIENCE: 

• Prior years of experience combined with technical education within the semiconductor industry 
• Expert level experience producing quality firmware 

ACADEMIC CREDENTIALS: 

• Bachelors or Masters degree (preferred) in Computer Science, Computer Engineering, Electrical Engineering, or equivalent 

LOCATION:

Singapore

THE ROLE:

We are seeking a dynamic Sales Director to lead our APJ regional strategy and drive demand for AMD-based HP Inc. products. In this role, you will define and execute AMD’s sales strategy, build strategic partnerships, and develop market approaches for nominated accounts. You will also lead and mentor an extended sales organization of sales professionals across multiple geographies. Your primary success metric will be winning market share and driving sales growth for 'One AMD', achieving or exceeding AMD’s Annual Operating Plan (AOP).

THE PERSON:

We’re looking for someone who brings:

• A relentless drive to win, backed by strong business acumen
• Proven leadership skills to motivate, mentor, and retain top talent across diverse regions
• Confidence, maturity, and integrity in all interactions
• An open, collaborative communication style with executive presence
• Trustworthiness and professionalism in dealings with customers, colleagues, and stakeholders
• Ability to listen and translate customer needs into actionable strategies
• Strategic vision and long-term planning capabilities
• International business experience across diverse cultures and geographies

KEY RESPONSIBLITIES:

• Define and implement Sell-Through and Sell-Out strategies and account plans to meet or exceed AMD’s AOP goals across APJ (Australia-New Zealand, Southeast Asia, Korea, Japan, India)
• Mentor and develop regional sales managers to drive revenue growth and market share
• Maintain sales hygiene through timely pricing submissions and accurate forecasting in SFDC
• Execute regional sales strategies for Enterprise, Government, Education, SMB/MM, and Consumer segments for HP Inc. 
• Grow Consumer Client & Commercial segments, including Workstations, Client PCs, any other relevant HP Inc products
• Collaborate with AMD country sales teams to drive end-customer bids and partner opportunities
• Oversee quarterly MDF budgets across APJ in alignment with HP Inc.  category and alliance teams
• Build and expand relationships with key internal and external C level stakeholders
• Establish quarterly business reviews with HP Inc. leadership and AMD executives
• Work closely across all internal stake holders to ensure operational efficiency 
• Identify new market opportunities and provide insights to AMD design-in and business unit teams
• Analyze market share trends, assess risks, and learn from key wins and losses
• Frequent travel required

PREFERRED EXPERIENCE:

• Leadership: Proven success in building and leading high-performing global teams
• OEM Sales: Experience in global sell-out or product sales, ideally in semiconductors for enterprise and commercial segments
• Partner Engagement: Strong relationships with MNCs/OEMs
• Organizational: Effectiveness in cross-matrix environments
• Product Expertise: Deep knowledge of Client PCs and Datacenter solutions
• Strategic Insight: Understanding of market dynamics and software ecosystems

ACADEMIC CREDENTIALS:

• Bachelor’s degree in Electrical Engineering or a relevant technical field; Master’s degree (MSEE) or MBA preferred.

LOCATION:

Singapore

THE ROLE: 

In this role, you will work closely with other firmware engineers, developers and architects across various IPs in designing and implementing firmware that spans pre-silicon and post-silicon for all AMD SoCs.  

THE PERSON: 

You are passionate about firmware development with creative and effective problem-solving skills, a motivated, self-starter who can work both independently and collaboratively in fast paced environments.  You have excellent technical communication, interpersonal and leadership skills. 

KEY RESPONSIBILITIES: 

• Design, develop, debug, verify and/or validate firmware, software and/or hardware 
• Participant in day-to-day firmware development work 
• Provide consultation to internal and external customers regarding AMD features and programming requirements 

PREFERRED EXPERIENCE: 

• Prior years of experience and/or education within the semiconductor industry 
• Experience producing quality firmware 

ACADEMIC CREDENTIALS: 

• Bachelors or Masters degree (preferred) in Computer Science, Computer Engineering, Electrical Engineering, or equivalent  

LOCATION:

Singapore

THE PERSON:

• Demonstrated ability to lead field sales teams and deliver pipeline conversion
• Experience with CSP products across AWS, Azure and Google Cloud Platform (GCP).
• Experience building executive relationships with the largest cloud adopting accounts.
• An understanding of data-center solutions and knowledge of sales cycle and motion for customers choosing cloud solutions
• Strong organization, presentation (both virtual and in-person), communication, and account management skills
• Capacity to travel and be customer facing up to 50%.

KEY RESPONSIBILITIES:

• Build and convert AMD EPYC based cloud consumption pipeline in APJ, aligned to sales targets
• Manage a team of cloud specialists and orchestrate their sales strategies and execution
• Partner with stakeholders in APJ regional sales, CSP global account teams, and business unit partners to deliver cloud consumption results
• Interact directly with customers during the sales cycle to build trusted advisor status and positive business outcomes from the use of AMD technology in the cloud.
• Travel to events and meetings as needed to support your team and manage sales opportunities.

PREFERRED EXPERIENCE:

• Proven track record leading sales teams selling technology to enterprise customers
• Experience working with/for a major Cloud Solution Provider (GCP, AWS, Azure, Oracle)

ACADEMIC CREDENTIALS:

• University or four-year college degree in Business or equivalent experience

OCATION:

Singapore

THE ROLE: 

As a Product Development engineer, you will collaborate with various Product Development Groups to bring-up and ramp new products which include Plan, debug and handling manufacturing and characterization test programs for next-generation AMD microprocessors. 

THE PERSON: 

A successful candidate is one who can perform in a role that requires accountability for accuracy, reliability and completeness of assignment results critical to the project’s success.  

KEY RESPONSIBILITIES: 

• Validate new product features, test conditions, test methodologies, and test contents during first silicon bring-up 
• Post Silicon Bring up of Test patterns leading to optimization for mass production enablement 
• Analysis of part failures leading to test improvement 
• Test pattern & test flow development, debug, test and characterization 

PREFERRED EXPERIENCE: 

• Knowledge of scripting languages such as Perl, Ruby, shell script 
• Good understanding of Linux, Unix or Windows OS 
• ATE (Automatic Test Equipment) test experience 

ACADEMIC CREDENTIALS: 

• Bachelor’s or Master’s in electrical engineering, computer engineering, or comparable disciplines 

THE ROLE:

Join a global package reliability team that drives package and board-level reliability activities across AMD’s IC and graphics-card products that employ advanced flipchip and chiplet package constructions. The expanding Singapore Package Reliability Lab requires a candidate to perform component/board-level reliability stress testing of AMD’s leading-edge packages.

THE PERSON:

A highly motivated Reliability Engineer with good project management skills which are crucial when collaborating with various teams across AMD. A strong and effective communicator, both verbal and written, which are essential when working with a global team. A proactive, outstanding teammate who focuses on teamwork, team building, and growing team success.

KEY RESPONSIBILITIES:

• Execute package qualifications, reliability assessments, and engineering evaluations.
• Coordinate package qualification efforts for new products, designs, materials or processes and other logistic activities.
• Perform and assess electrical, mechanical, visual and acoustic microscopy results.
• Validate reliability test failures and conduct in-depth debug and root-cause identification.
• Develop open/short test program to support CPI (chip-package interaction) testing.
• Responsible for quality and timeliness of results for assigned tasks.

PREFERRED EXPERIENCE:

• Knowledgeable in statistical analysis
• Experience with scripting languages (C, C++, Java, Ruby, Perl, Python)
• Proficient in Window, Unix, and Linux operating systems

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in related discipline preferred

THE ROLE:

We are seeking a motivated and detail-oriented Verification Engineer to join our DDR PHY IP development team. As an entry-level engineer, you will play a key role in verifying high-performance DDR PHY intellectual property used in cutting-edge SoCs across data center, mobile, and automotive markets. You’ll work closely with experienced design and architecture teams to develop robust verification environments, ensure design correctness, and contribute to silicon success

THE PERSON:

The ideal candidate is a passionate and driven engineer with a strong foundation in digital design. You are detail-oriented, eager to learn, and excited by the challenge of working on complex DDR PHY IP used in high-performance systems. You thrive in collaborative environments, take initiative in solving technical problems, and communicate clearly with both design and verification teams. Above all, you are motivated to grow your expertise in memory interface technologies and contribute to delivering reliable, high-quality silicon products.

KEY RESPONSIBILITIES:

• Develop and maintain UVM-based verification environments for DDR PHY IP.
• Write and execute test plans, directed and constrained-random tests, and functional coverage models.
• Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues.
• Create and maintain verification collateral, including testbenches, checkers, and scoreboards.
• Perform regression runs, track functional coverage, and ensure full design verification closure.
• Contribute to automation scripts for regression, data analysis, and verification efficiency improvements.

PREFERRED EXPERIENCE:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Strong understanding of digital design fundamentals (clocking, timing, state machines, analog design basics).
• Experience with SystemVerilog and UVM (academic or internship exposure preferred).
• Familiarity with simulation tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
• Basic understanding of DDR memory protocols and PHY architecture is a plus.
• Proficiency in scripting languages (Python, Perl, or TCL) for automation.
• Excellent analytical, debugging, and communication skills.
• Enthusiasm for learning and problem-solving in a collaborative, fast-paced environment.

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in related discipline preferred