Total 2,825 Senior Executive operations engineer job vacancies

We are seeking a high-caliber Senior DevOps Engineer to lead the optimization and management of our high-concurrency trading infrastructure. You will be a key bridge between Development and Operations, ensuring the low-latency, high-throughput performance of our matching engines and wallet services. This role demands a strong focus on automation, scalability, and "Infrastructure as Code" (IaC) in a multi-cloud environment.

Key Responsibilities:

Trading Core Business Support

• Customize low-latency and high-throughput system tuning for core components, including Matching Engines, Wallet Services, and Market Data feeds. Provide architectural stability and scalability advice during the design phase.

Cloud-Native & Automation

• Manage multi-cloud resources (AWS, GCP, Azure, Alibaba Cloud) using IaC tools (Terraform, Ansible, Pulumi) to avoid vendor lock-in. Oversee Kubernetes (K8s) clusters and optimize microservices elasticity using Helm/Operator.

CI/CD Pipeline Design

• Build and maintain GitOps workflows (GitLab CI/ArgoCD) to achieve rapid deployment and near-instant rollback capabilities.

Full-Stack Observability 

• Integrate Prometheus, Grafana, ELK, and OpenTelemetry to build a comprehensive monitoring system that detects transaction delays and fund anomalies in real-time.

DevSecOps & Security

• Integrate security scanning (SonarQube/Snyk) into pipelines. Maintain WAF, firewall, and IDS/IPS strategies in production to ensure compliance with external audits.

Incident Management

• Participate in and manage the 7x24 on-call rotation. Act as an Incident Commander during production issues and drive Root Cause Analysis (RCA) to prevent recurrence.

Job Requirements:

Professional Experience

• Substantial experience in IT infrastructure, with a significant focus on DevOps or Site Reliability Engineering (SRE). 
• Background in crypto exchanges, high-frequency trading (HFT), or high-concurrency Fintech platforms is highly preferred.

Technical Skills

• Expert-level Linux system administration and proficiency in Shell/Python scripting for kernel-level performance troubleshooting.

• Hands-on experience with CI/CD toolchains (GitLab CI, ArgoCD) and IaC (Terraform, Pulumi).Deep expertise in Kubernetes ecosystems (Helm, Kustomize, Operator).
• Familiarity with DevSecOps practices and cloud security best practices (SonarQube, Snyk).

Soft Skills

• Strong ownership and the ability to remain calm and decisive under extreme market volatility.
• Excellent cross-departmental coordination skills to bridge the gap between Dev and IT.
• Highly self-driven and adaptable to a professional remote or hybrid collaboration model.

Drive feature delivery and reliability for OpenWrt-based routers; be the go-to engineer for complex firmware issues and cross-discipline integration with RF and hardware teams.

Key Responsibilities:

• Lead design and implementation of medium-to-large features (driver tweaks, hostapd enhancements, ACS/DFS improvements, power management).
• Own troubleshooting of field escalations and complex regressions; design fixes and tests.     
• Improve CI/CD for firmware builds, add automated RF test hooks and performance benchmarks.       
• Mentor junior engineers, perform thorough code reviews, and champion best practices.
• Collaborate with RF/HW/product on calibration flows and factory provisioning.

Must-have:

• 5+ years embedded Linux experience with 3+ years on OpenWrt or similar embedded distributions.     
• Strong C, shell, and Python; experience with kernel debug (dmesg, perf, ftrace) and device trees.     
• Solid knowledge of Linux networking (bridging, ip, netfilter/nftables, qdisc) and wireless stacks (mac80211/hostapd).
• Experience shipping production firmware and participating in release processes.

Nice-to-have:

• Driver experience on Qualcomm/Atheros platforms, familiarity with ath9k/ath10k.
• Experience with Wi‑Fi roaming, mesh (802.11s), MLO or Wi‑Fi6 features.
• Background in OTA/A-B updates, secure boot, or telemetry stacks.
  

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.

Role Summary

As a Senior Member of Technical Staff (SMTS), you are a module‑level CMP technical authority, responsible for defining CMP technical direction, leading FOAK developments, and driving cross‑functional execution across NAND nodes. As a SMTS (Senior Member of Technical Staff), you will be a part of revolutionary Next Generation NAND research & development CMP team driving Advanced NAND and CMP technology forward. The position promises ample opportunities for innovation, collaboration and testing a new dimension and scaling with Next Generation NAND. A SMTS CMP Engineer is a senior individual contributor responsible for defining, developing, and transferring advanced CMP processes for Micron NAND technologies. You will work directly with process integration and other process areas such as Wet Etch, CVD, Diffusion, Metals, Lithography & Dry Etch. You will work on state of the art and best in class CMP chambers & own the process roadmap to meet program and yield goals.

Main Responsibilities

• Own and lead key NAND CMP process modules, translating technology challenges into executable roadmaps across current and future nodes

• Drive cross‑functional execution across Technology Development, Process Integration, Manufacturing, and Equipment teams

• Lead FOAK CMP process development, including recipe architecture, control strategies, and integration alignment

• Ensure process robustness and manufacturability through run‑to‑run controls, SPC, qualification execution, and risk mitigation

• Resolve complex yield, defectivity, and integration issues using model‑based and data‑driven problem solving

• Define and execute process‑level hardware strategies in collaboration with equipment suppliers

• Act as a CMP technical leader, mentoring engineers, influencing adjacent process roadmaps, and communicating technology status and plans to senior stakeholders

<>·

Other Responsibilities

• Mentor engineers through structured development; build SME pipelines; publish internal papers/BKMs and present to senior leadership; uphold Micron’s technical leadership expectations

• Integrates AI assisted tools and insights into daily work to improve efficiency, quality, or effectiveness, exercising sound judgment and complying with organizational standards and legal requirements.

• Contributes to a culture of continuous improvement by identifying, testing, and sharing AI enabled enhancements within one’s scope of work.

Candidate Profile

Minimum Qualifications / Experience

• PhD ≥12 yrs, or Master’s ≥15 yrs, of relevant experience in
  Electrical Engineering, Materials Science, Chemical Engineering, Physics, or related field,

• Experience in CMP Process Development

• Deep expertise in CMP chemistry, physics, and integration

• Publications/patents and strong record of technical contributions.

Must-Have Technical Skills

• In‑depth expertise in CMP fundamentals, including pad–slurry–wafer interactions, slurry chemistry at a mechanistic level, and pattern density/layout effects

• Strong understanding of multiple CMP process types (e.g., metal, dielectric, barrier/hardmask, poly‑Si/Si CMP)

• Extensive hands‑on experience with advanced 300 mm CMP OEM platforms, including driving hardware capability, throughput, and cost improvements

• Proven expertise in statistical process control (SPC), data analysis, and qualification methodologies

• Ability to independently drive complex technical execution, resolve yield and defectivity issues, and influence cross‑functional teams

Must-Have Soft Skills

• Demonstrated technical leadership in problem solving, with experience leading complex or multi‑disciplinary technical projects

• Strong ability to influence without authority across process integration, equipment, and manufacturing teams

• Clear and structured technical communication skills, including written documentation and stakeholder updates

• Strong analytical mindset with disciplined, data‑driven decision making

Embody Micron’s core values:

• People – Respect, develop and empower others

• Innovation – Drive continuous improvement and breakthrough thinking

• Tenacity – Show grit and determination

• Collaboration – Build trust and foster teamwork

• Customer Focus – Deliver excellence and value

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.
  

  Performs hardware, software, semiconductor design or telecomm engineering assignments. This job mapping should be used only if the position cannot be mapped specifically to other design/development engineering jobs.

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.

• Well Established Security Inspection Solutions Company

• Salary: $4500 - $5500

• Working Hour: Monday - Friday (8.30am – 5.30pm)

• Company Location: Jurong East

• Variable bonus + Excellent Wellfare

Job Scope:

• Lead a Project Team of consultants, contractors, developer in daily-site activities
• Conduct project briefing and kick start meeting
• Responsible for periodic progress reports
• Evaluate the master program and monitor work progress
• Identify potential or actual causes of delay and take preventive or remedial actions
• Monitor submissions and clearances from relevant authorities
• Assist on documentations and make recommendation to clients for award of contracts
• Check safety management system and conduct periodic safety inspection
• Conduct feasibility studies and recommendations on the development concept, preliminary program and budget
• Identify and resolve site technical problems
• Supervise site works to achieve good quality
• Assist in investigating and liaising with public and the relevant authorities for public feedback

Requirement:

• Diploma in IT Engineering, Civil Engineering, Architectural or equivalent
• 2 - 3 years of relevant working experience in project management

Candidates are encouraged to apply this position via ApplyNow button with the following information in the resume:

• Work experiences and job responsibilities
• Current and Expected salary
• Reason for leaving
• Date of availability
• Education background

We regret that only shortlisted candidates will be contacted.

YEOW CHANG FU (R23118759)

EA Recruitment Pte Ltd

EA License No: 21C0492

• Support theproduction of scalable and optimised AI or machine learning (ML) models.
• Focus on building algorithms for the extraction, transformation and loading of large volumes of real-time, unstructured data to deploy AI or ML solutions from theoretical datascience models.
• Run experiments to test the performance of deployed models, and identifies and resolves bugsthat arise in the process.
• Work in a teamsetting and apply knowledge in statistics, scripting and programming languages required by the firm.
• Work with therelevant software platforms in which the models are deployed.

Mandatory Skills Description:

• Minimum of 6 to 9 years of experience to implement the solution
• Multi-Agent System Design & Orchestration
• Full-stack AI Integration (Frontend to Backend)
• AI Safety, Guardrails & Governance
• Enterprise Application Integration & AI Orchestration
• High-Scale Vector Database Management
  
  
  

We are seeking an experienced Project Engineer / Senior Project Engineer to lead and manage EPC project packages involving Ultra Pure Water (UPW), Industrial Water, and Wastewater Treatment facilities. The successful candidate will be responsible for project delivery, stakeholder management, financial performance, contract administration, risk management, and coordination of multidisciplinary teams throughout the project lifecycle.

Candidates must possess strong experience delivering Ultra Pure Water (UPW) and Wastewater Treatment projects. Experience in semiconductor, electronics, pharmaceutical, data centre, or high-purity process industries will be highly preferred.

Key Responsibilities

Project Management & Delivery

• Develop, implement, and adapt project execution strategies for complex EPC projects.
• Manage multiple project packages and report directly to the Project Manager.
• Ensure projects are delivered safely, on schedule, within budget, and in accordance with contractual and technical requirements.
• Take ownership of project financial performance, margins, quality, technical compliance, and delivery milestones.
• Prepare, monitor, and manage project budgets, forecasts, cost reports, and resource plans.

Stakeholder & Contract Management

• Manage relationships with clients, consultants, subcontractors, suppliers, and project partners.
• Lead commercial discussions, variation management, claims management, and contract administration activities.
• Coordinate effectively with internal departments including Engineering, Procurement, Construction, Commissioning, and Finance.
• Escalate critical project issues and risks where appropriate.

Leadership & Risk Management

• Lead and coordinate multidisciplinary project teams to achieve project objectives.
• Foster collaboration, accountability, and continuous improvement across project teams.
• Identify, assess, mitigate, and manage project risks and opportunities.
• Ensure compliance with Quality, Health, Safety and Environmental (QHSE) requirements.

Systems, Reporting & Continuous Improvement

• Prepare project reports, management updates, and performance reviews.
• Utilize SAP and other project management systems to manage project execution.
• Ensure compliance with ISO standards, company procedures, and project governance requirements.
• Support implementation of project execution methodologies and lessons learned programs.

Qualifications & Requirements

• Bachelor's Degree in Engineering or a related discipline.
• Minimum 10 years of project management experience within EPC, industrial, utilities, water treatment, or process plant environments.
• Mandatory experience managing Ultra Pure Water (UPW) and Wastewater Treatment projects.
• Proven experience managing large-scale multidisciplinary project packages independently.
• Strong commercial, contractual, and financial management skills.
• Experience managing clients, subcontractors, suppliers, and consultants.
• Familiarity with SAP and project management systems.
• Strong leadership, communication, and stakeholder management abilities.
• PMP Certification will be an advantage.

Preferred Industry Experience

• Semiconductor Manufacturing Facilities
• Electronics Manufacturing Plants
• Pharmaceutical Facilities
• High-Purity Process Facilities
• Data Centres
• Industrial Water and Wastewater Treatment Plants

• Manage, lead and support in C&S/Technical design functions; be in-charge for all (C&S) civil/structural site-based design matters being tasked for an MRT Project
• Attending and being proactive in design coordination meeting with consultants / client
• Ensure drawing registry is maintained and latest drawings / BIM models are available for all parties involved
• Ensure transmittal forms / emails are issued for latest drawings / BIM models,
• To study & review drawings / specifications in identifying discrepancies and issue queries to consultants accordingly
• Resolve technical issues on drawings and liaise closely with Consultants, all trades and authorities.

Requirements

• Bachelor's Degree and above in Civil/Structural or relevant engineering discipline
• At least 5-7 years of prior experience with a contractor or consultant environment
• Comfortable to work on 5.5-days Workweek

If the role resonates with you and your professional experience complements the responsibilities listed, send your resume to koh.dickson@bayesrecruitment.com

Dickson KOH, EA Registration R1103367

www.bayesrecruitment.com

• Well Established Company
• Excellent Welfare and Benefits + Career progression
• Basic $ 4500 to $ 6000 + AWS + VB
• Working location: North-East
• Working Hours: Monday to Friday (8:30am to 5:30pm)
• Must have C / C++

Job Responsibilities:

• Responsible for software prototyping, requirement analysis, design, development, test, system integration and site integration for developed applications
• Design, configuration, test, integration and maintenance of Automation & SCADA Systems and applications
• Provide technical, deployment and commissioning support to Project Teams and Customers
• Maintain and enhance software applications in both functionality
• Provide software support via on-site troubleshooting, testing and tuning of applications, software, network, protocols and communication issues

Requirements:

• Diploma/Degree in Electronics Engineering or Computer Science
• Experienced with two or more languages such as C/C++, C#, Python
• Experienced in at least one scripting language sch as Python, bash, ksh, bat, ps
• Experience in real tome/embedded system
• At least 2-3 years experience in C/C++ and at least 1 full SDLC
• Knowledge/Experience with SCADA protocols, RDBMS, REST, MQTT are desired

Candidates are encouraged to apply this position via Apply Now button with the following information in the resume

• Work experiences and job responsibilities
• Current and Expected salary
• Reason for leaving
• Date of availability
• Education background

We regret that only shortlisted candidates will be contacted.

NG DIAUM YEE (R2198031)

EA Recruitment Pte Ltd

EA License No: 21C0492

Roles & Responsibilities

Job Summary

Manage customer orders and enquiries, handle cargo documentation, coordinate with customer and operations teams, and ensure timely delivery while maintaining compliance with client procedures and preparing regular reports.

Responsibilities

• Process customer orders accurately and within required timeframes to meet delivery schedules

• Respond to customer enquiries and provide clear, timely sales quotations

• Manage customer requests efficiently to maintain smooth service operations

• Prepare and handle cargo documentation for import, export, and local trucking shipments

• Close job files monthly to ensure accurate record-keeping and reporting

• Liaise and coordinate with drivers, clients, and suppliers to ensure timely and smooth delivery of goods

• Ensure all activities comply with client’s standard operating procedures to maintain quality and consistency

• Coordinate with drivers and operations teams to complete orders fully and on schedule

• Prepare and submit monthly, weekly, and daily reports as required to track performance and operations

• Perform other ad-hoc duties as assigned to support team and operational needs

Key Responsibilities

• Handle end-to-end airfreight operations for both import and export shipments.
• Manage export shipments: booking, MAWB/HAWB preparation, permits, and coordination with airlines/co-loaders.
• Manage import shipments: monitor arrival, arrange clearance, coordinate delivery and follow up with customers.
• Prepare and send quotations to overseas agents and customers.
• Source and compare co-loader / airline rates to ensure competitive pricing.
• Liaise with airlines, co-loaders, transporters, warehouse and customers for smooth operations.
• Monitor shipment status and provide timely updates on arrivals, delays, or issues.
• Ensure proper documentation and compliance with customs requirements.
• Handle billing, job costing and data entry accurately.

Requirements

• Experience in airfreight import & export operations preferred.
• Knowledge of MAWB/HAWB, permits, customs clearance.
• Able to check rates and do pricing/quotation independently.
• Good coordination and communication skills.
• Able to multitask and handle fast-paced shipment requirements.
• Familiar with freight systems is an advantage.

Work Location: Changi Airfreight Centre

Purpose and main tasks

1. Handle and supervise the accurate and timely movement of ocean freight to- and from specific locations within the service standards agreed with the Customer

2. Handle and supervise all Vendor facing communication and shipment related internal communication between DSV stakeholders

3. Supervise the execution of country specific customs clearance processes

4. Supervise multimodal FCL, LCL pre/on-carriage services (Hinterland Transportation) by truck, rail or barge

5. Create solutions- and pricing for FCL, LCL ocean freight Hinterland Transportation services for internal Ocean Operations-, Trade- and Sales Teams

6. Participate in ad-hoc projects related to business process improvement (Internal and External).

7. Take on additional tasks (e.g. create / update ISO procedures) during department performance review and/or annual scheduled events (e.g. audits) as assigned by superiors.

8. Perform value-added task within the scope of the function to meet customer requirements and changes made in the operations process

9. Monitor and ensure all customs permit declaration are in compliance with Singapore Customs Regulations and Procedures.

10. Monitor individual & team performances and balance workload

11. Escalate unresolved issues to next management level

Accountable

1. Ensure timely activation and/or creation shipment in TMS (TANGO)

2. Activate and/or create shipment in TMS (TANGO)

3. Ensure the accuracy check is conducted

4. Ensure all operational SOPs are properly followed

5. Ensure all operational KPIs are achieved

6. Initiate credit check for Consignee and follow up on credit issues with Finance Team

7. Check actual shipment arrival date with Carrier and confirm in TMS (TANGO) - as applicable

8. Receive Carrier's Arrival Notice

9. Update shipment arrival information in TMS (TANGO)

10. Ensure interaction with carriers, CY (Container Yard), port and customs authorities and external customs broker is properly executed

11. Ensure interaction with CFS (and port and customs authorities if applicable) is properly executed

12. Check container arrival at CY (Container Yard) and confirm in TMS (TANGO)

13. Perform required interaction with CY (Container Yard) and port authorities - as applicable

14. Request cargo release information, documents and freight invoice from Carrier - as applicable

15. Receive Original HBL from Consignee and confirm receipt in TMS (TANGO) - as applicable

16. Ensure that Original MBL is surrendered to Carrier at origin or destination - as applicable

17. Provide self-pickup instructions to Consignee - as applicable (Sender shown as "Customer Management")

18. Provide shipment details (manifest) to customs authorities - as applicable

19. Provide "Change Advice" to Consignee - as applicable

20. Continuously Monitor container pickup status at CY (Container Yard)

21. Confirm self-pickup details in TMS (TANGO) - as applicable

22. Ensure all relevant documents are received and/or uploaded to digital archive (ODM)

23. Ensure and Provide delivery information to Trucking Vendors (if merchant's haulage) and/or to Carrier (if Carrier's haulage), and self-pickup instructions/ delivery details are provided to consignees.

24. Receive pick up/delivery requests from Customer Management Teams via TMS (TANGO)

25. Determine optimal vendor, routing and price

26. Provide delivery/pick up/drayage instructions to vendors

27. Confirm container delivery to the CY (Container Yard)

28. Update TMS (TANGO) with truck / vendor details - as applicable (ideally done electronically)

29. Identify match-back and proactively combine load opportunities

30. Perform required interaction incl. document transfer with external customs broker - as applicable

31. Supervise the execution of country specific Import customs clearance processes

32. Ensure customs related documents are prepared and submitted to relevant government authorities and/or Customs and/or Customs Broker to obtain customs permit and/or certificate of origin - as applicable

33. Accuracy check of the customs required data entry

34. Solve and/or escalate issues resulting from communication with Customs and/or Customs Broker and/or government body

35. Direct communication with Customs and/or Customs Broker and/or government body - as applicable

36. Check shipment delivery status and confirm in TMS (TANGO) - as applicable

37. Check empty container return to CY (Container Yard) and confirm in TMS (TANGO) - as applicable

38. Manage and resolve all disputes and issues with vendors

39. Ensure timely and accurate completion of activities in TMS (TANGO)

40. Create and verify income /cost accruals in TMS (TANGO), including standard and exceptional and accessorial income reserves and cost accruals.
41. Ensure demurrage & detention details are provided to Customer management in a timely manner

42. Ensure compliance with Customer specific KPI's - as applicable

43. Set and provide internal recommended sell rates (as directed by Regional resp. Cluster/Country Heads of Trade and Country Heads of LCL)

44. Ensure vendors provide preset, automated, electronic milestone transmission into systems - visible in TMS (TANGO)

45. Ensure electronic connectivity of vendors with DSV systems for dispatching and invoicing - executable in TMS (TANGO)

46. Select, and negotiate with, internal- and external service providers based on pricing, preset service and electronic connectivity standards

47. Proactively manage performance of vendors through setting and monitoring of transparent, uniform KPIs

48. Conduct regular and documented performance reviews with vendors including actionable continuous improvement measures

49. Supervise "cost control" in TMS (TANGO) - as applicable

50. Request update from/with MDM Team (Master Data Management) as applicable

51. Receive and check hinterland vendor invoices then forward to OA for posting

52. Ensure each file Profit + Loss statement shows a profit and escalate “Loss” file information to Customer Management Team - as applicable

Responsible

1. Ensure operations is executed efficiently and with high quality

2. Select service providers based on portfolio, cost and service quality

3. Ensure that digital channels are used when communicating with vendors

4. Support a positive, attractive working atmosphere and office environment

5. Establish regular communication with the customer management and trade management in regard to carrier selection

6. Establish regular communication with the customer management and LCL management in regard to CFS and pre-carriage service providers selection

7. Escalate service/ technical issues as needed

8. Handle discipline & grievance cases for direct reports

9. Involved in the exercise of performance appraisal as a supervisor or leader

10. Participate in recruitment process to attract and identify potential candidates

11. Responsible for on-job training and career progress for direct reports

Required skills

1. Ability to lead and manage team

2. Ability to multi-task

3. Effective communication skills and professional communication etiquette

4. Fluency in written and spoken English

5. Fluency in written and spoken [local] language

6. Perform well under pressure

7. Strong computer (Windows PC) skills

8. Typing skills (at least 30 words per minute)

9. Decision-making and problem-solving skills

10. Ability to prioritize and manage time

11. Attention to detail and accuracy

12. Organizational skills

13. Must work well within a team

Required education

1. Diploma in business/operation management/transportation/logistics/relevant discipline is preferred.

Required experience

1. Minimum 3 years of working experience in the sea freight industry is preferred

2. Relevant experience in managing a team is necessary.

3. Knowledge of ocean freight, international trade and relevant laws, regulations, Supply Chain processes and procedures will be preferred

4. Self-driven individual with high degree of professional integrity

5. Ability to communicate at all levels of business and across cultural / National boundaries

6. Good analytical skills – supply chain process

7. Possess good communication and presentation skills

8. Ability to lead cross functional teams

Job Responsibilities

• Support in overseeing daily inbound warehouse operations

• Manage inbound activities including goods receiving, returns processing, inspections, and system updates

• Lead and coordinate the inbound team to ensure smooth workflow and operational efficiency

• Monitor operational performance and ensure service standards and KPIs are achieved

• Liaise with internal stakeholders, contractors, and external parties on inventory, returns, and operational enquiries

• Handle inventory discrepancies, exceptional cases, and ad-hoc operational issues

• Prepare and maintain monthly operational and performance reports

• Ensure proper documentation, filing, and record management for easy retrieval and audit purposes

• Maintain warehouse housekeeping standards and ensure compliance with workplace safety regulations

• Support manpower planning, staff training, and shift operations when required

Job Requirements

• Diploma in Logistics, Supply Chain, Warehouse Management, or related field

• Minimum 2–3 years of experience in warehouse or logistics operations

• Familiar with inventory management and warehouse processes

• Good organisational and problem-solving skills

• Proficient in Microsoft Office and warehouse management systems

• Able to work independently in a fast-paced environment

• Strong communication and coordination skills

Attention to: Debbie Tan (debbie.tan@elitez.asia)

By submitting any application or résumé to us, you will be deemed to have agreed and consented to us disclosing your personal information to prospective employers for their consideration.

We regret to inform you that only shortlisted candidates will be notified. All applications will be treated with the strictest confidence.

Elitez Pte Ltd | EA Licence: 16C8004 | Debbie TAN | Registrations No: R26159853