Total 159 process development engineer job vacancies in Bengaluru

About Us 

At Karbon, we’re building the future of fintech with our flagship product, AI Accountant. By combining deep financial expertise with cutting-edge AI, we simplify accounting, credit, and financial operations for India’s fastest-growing businesses. Backed by Y Combinator and leading global investors, Karbon powers 3000+ startups, unicorns, and enterprises. 

Job Summary 

The role involves supporting the Growth team by conducting engaging product demos for prospective customers, onboarding them to the AI Accountant platform, and ensuring successful activation and training for sustained product usage. 

Key Responsibilities 

• Support inbound/outbound sales via email, LinkedIn, and calls to generate qualified leads.
• Conduct product demos for prospective and existing customers
• Manage and update CRM entries, track conversations, and support timely follow-ups.
• Prepare basic pitch decks, sales notes, competitor analysis, and market insights.

• Collaborate with sales and onboarding teams to ensure smooth lead-to-customer transitions.

Must-Have Skills 

• Excellent communication and presentation skills. 

• Strong interest in sales, customer success, and product-led growth. 

Good-to-Have Skills 

• Basic understanding of SaaS products and workflows. 

• Ability to manage multiple priorities and deliver within deadlines. 

• Proactive approach to learning and improving customer engagement. 

Our Way of Life — The Karbon Values 

C – Collaborate to Win 
We win together, not alone. We listen, challenge with care, and move as one team. 

E – Excel Relentlessly 
"Good enough" isn’t good enough. We push for world-class in everything we do. 

O – Own It End-to-End 
We think like founders. We take full responsibility for outcomes—not just tasks. 

Perks & Benefits 

• Upskilling Policy: Access to courses, tools, and resources to keep learning and growing. 

• Team Outings: Offsites and outings to celebrate milestones and build deeper bonds. 

• Engagement Initiatives: Hackathons, open demos, and game nights—designed to spark creativity and fun. 

• Flexible Work-from-Home: Up to 12 WFH days every 6 months. 

• Menstrual WFH: Women employees can avail up to 3 WFH days per month. 

• Mobility Benefits: Relocation support and travel allowance. 

• Parental Support: Maternity, paternity, and adoption leave. 

 If you’re passionate about building world-class fintech products, love solving challenging engineering problems, and thrive in fast-moving environments — join us at Karbon.

As a Pricipal Emulation Engineer in the ASIC Emulation team, you will be responsible for Emulation builds, sanity test suite & methodology. 

• Providing technical leadership and expertise to define requirements for Emulation and Emulation IP development.
• Create emulation models from RTL / Netlist. Develop hardware collateral to be integrated with the Palladium / FPGA emulation mode.
• Experience in Palladium or Zebu Platforms Automation and increase process efficiencies.
• Collaborating cross-functionally to optimize emulation workflows and standardize methodologies.
• Work with extended teams to debug environment and drive cross-functional testing (Firmware, Software, Verification and Design)
• Triage failures with design, verification, firmware, software teams.
• Mentoring and guiding junior engineers, fostering a culture of collaboration, innovation and continuous improvement.

Skills Required:

• Working knowledge of Linux/Unix environment and shell scripting
• Excellent debugging and problem-solving skills with simulation and emulation environments.
• Cross-Functional Collaboration: Ability to work closely with design, validation, firmware, and physical design teams to resolve system-level issues.
• Strong team player, able to collaborate effectively across architecture, design, and validation teams.

• Development of C++/SystemC models for complex ASIC IPs, SOCs and Flash Memories.
• Create System Level Tests and/or Standalone Unit Tests and verify the models.
• Lead and Guide team in the project activities.
• Keen on schedule and quality of the deliverables.
• Timely support to the stakeholders enabling software bring-up.

Full-stack developer responsible for analysis, design and development of .NET and WPF applications part of a high impact software product suite.

JOB DESCRIPTION

Requirements:

Mandatory Skills:

• 5 to 8 years of experience developing software using .NET and WPF.

• Proficient in C#, .NET, WPF/XAML, Web APIs, LINQ, Entity Framework, SQL.

• Experience working on at least one SOA or microservices architecture style software product.

• Good understanding of UML, object-oriented programming (OOP) and Object Oriented Design principles.

• Strong knowledge of software development best practices. Passion for code quality to write well-factored, optimized, unit tested, reliable code.

• Knowledge about performance management to prevent performance issue in C# or SQL.

• Excellent debugging skills to troubleshoot issues reported from production environment.

Preferred Skills (but not mandatory):

1. 2 years of hands-on WPF development experience and/or equivalent proficiency

2. Familiarity with Agile methodologies such as Scrum and Kanban, preferably in a scaled agile environment.

3. Experience with Test-Driven Development (TDD) or Acceptance Test-Driven Development (ATDD); familiarity with tools such as FitNesse or Postman is a plus

4. Exposure to developing and deploying applications on Microsoft Azure.

Personal Skills:

1. Strong analytical and problem-solving abilities.

2. Excellent verbal and written communication skills; capable of clearly articulating complex technical issues to various stakeholders.

3. Self-motivated, detail-oriented, and a reliable team player.

4. Comfortable working in a dynamic, international team environment

Full-stack developer responsible for analysis, design and development of .NET and WPF applications part of a high impact software product suite.

JOB DESCRIPTION

Requirements:

Mandatory Skills:

• 5 to 8 years of experience developing software using .NET and WPF.

• Proficient in C#, .NET, WPF/XAML, Web APIs, LINQ, Entity Framework, SQL.

• Experience working on at least one SOA or microservices architecture style software product.

• Good understanding of UML, object-oriented programming (OOP) and Object Oriented Design principles.

• Strong knowledge of software development best practices. Passion for code quality to write well-factored, optimized, unit tested, reliable code.

• Knowledge about performance management to prevent performance issue in C# or SQL.

• Excellent debugging skills to troubleshoot issues reported from production environment.

Preferred Skills (but not mandatory):

1. 2 years of hands-on WPF development experience and/or equivalent proficiency

2. Familiarity with Agile methodologies such as Scrum and Kanban, preferably in a scaled agile environment.

3. Experience with Test-Driven Development (TDD) or Acceptance Test-Driven Development (ATDD); familiarity with tools such as FitNesse or Postman is a plus

4. Exposure to developing and deploying applications on Microsoft Azure.

Personal Skills:

1. Strong analytical and problem-solving abilities.

2. Excellent verbal and written communication skills; capable of clearly articulating complex technical issues to various stakeholders.

3. Self-motivated, detail-oriented, and a reliable team player.

4. Comfortable working in a dynamic, international team environment

Staff Engineer, Digital Design role requiring 8+ years of experience of Digital design in Analog Mixed signal ICs for developing Power Management ICs as part of 2.6B$ Power Business Unit at Renesas. Primary responsibilities include leading team which will fully own defining the microarchitecture to developing all Digital components of power management ICs, starting from System requirements. Due to the complex nature of Chips and significant Analog as well as Digital contents, collaboration with cross-functional teams to ensure successful integration of Digital and Analog components in ICs, is a must. The candidate will work on a wide range of exciting and cutting edge PMICs, including Linear and Switching DC-DC converters powering the next generation of most sought-after phones and handheld devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.

Essential Functions:

• Must have experience of defining Dig-Ana boundary and Digital design scope for Power Management ICs/Analog intensive ICs
• Must have experience of defining the micro-architectures and sub-blocks for the ICs to ensure optimized Digital design, RTL design and Gate level netlist etc.
• Must be aware of Power Sensitive digital design and doing Power estimation for the Digital I/Ps
• Must be able to handle Clock Domain Crossing across multiple clock domains seamlessly and in a glitch free manner.
• Should have experience of OTP, MTP, Efuse read/writes, controller design and data bus handling, Register read/write, Trimming of Analog parts/functions etc.
• Should be able to create Sequences (including Power UP/Down) and State Machines and Transitions to/from any state to another based on the IC requirements.
• Should be an expert of one or more Power Chip Communication I/Ps and protocols e.g. I2C, PMBUS, SVI3, SVID etc.
• Should be able to implement and analyse filters & feedback loops in Digital, conversant with Z-domain analysis.
• Must have done multiple silicon debugs, root cause analysis of issues, design to silicon correlation etc.
• Should understand commonly used control loop architectures (Constant Freq, Constant ON/OFF Time, Current mode etc) and pros/limitations of each.
• Must be able to bring in innovative ideas to improve designs to meet challenging specifications and achieve better system performance.
• Should be able to setup Digital design flows and methodologies including checklists, reviews to ensure quality designs and take them all the way to Silicon success.

We are looking for a Staff Machine Learning Engineer to play a pivotal role as a technical leader within the LSS AI team. This role goes beyond building models- you will set the technical direction, own the AI roadmap, and lead initiatives that push the boundaries of what's possible in enterprise AI. You will combine deep research expertise with the ability to build production-grade ML systems at scale, partnering across engineering, product, and research to deliver transformative AI solutions.

At LinkedIn, our approach to flexible work is centered on trust and optimized for culture, connection, clarity, and the evolving needs of our business. The work location of this role is hybrid, meaning it will be performed both from home and from a LinkedIn office on select days, as determined by the business needs of the team.

Responsibilities

• Lead the design, development, and deployment of state-of-the-art ML systems across search, recommendations, generative AI, reinforcement learning, and LLMs for Sales Navigator.
• Define and drive the technical roadmap and architecture for end-to-end AI systems within LSS, ensuring scalability, reliability, and innovation.
• Research, fine-tune, and adapt large language models (LLMs) and build agentic AI systems that enable reasoning, planning, and decision-making for sales professionals.
• Partner with product, design, and other engineering teams to align AI solutions with business strategy and maximize impact.
• Drive cross-functional collaborations with horizontal AI and platform teams to leverage foundational tools and scale adoption of innovations across LinkedIn.
• Mentor and guide engineers, fostering a culture of craftsmanship, innovation, and technical excellence.
• Represent LinkedIn in external venues (papers, conferences, workshops) by showcasing advances in applied AI research and engineering.

We are looking for a Jira Administrator/Process Coordinator to act as the workflow enforcer and audit engine for a large-scale network consolidation program at a US-based Tier-2 Telco. The role governs the Jira pipeline, ensuring that only complete and validated data enters the engineering workflow and that every executed cutover is fully traceable to measurable financial outcomes. This position is ideal for professionals who excel at enforcing strict workflows, maintaining data integrity, and ensuring full traceability across complex transformation programs.

Responsibilities:

• Manage the intake funnel by enforcing strict data completeness requirements and rejecting Implementation Units (IUs) that lack mandatory information such as target subnets or legacy asset identifiers
• Package validated engineering outputs into structured release waves (Fix Versions/Releases) aligned with weekend migration schedules and CAB processes
• Ensure end-to-end traceability by linking every executed technical change to corresponding decommissioned legacy assets, providing a clear audit trail for financial ROI validation
• Monitor the T-Minus migration schedule and escalate logistical risks, vendor delays, or process blockers to the Project Manager to maintain factory velocity
• Maintain Jira hygiene by enforcing transition validators, custom fields, required workflows, and consistent issue lifecycle management across the program

We are looking for an Embedded Storage Firmware Engineer to design, develop, and maintain firmware for high performance storage devices and controllers. In this role, you will work close to the hardware, building reliable, high‑performance firmware that manages data movement and device behavior under real‑world workloads.

You will contribute across the storage firmware stack, including boot, device initialization, data path, error handling, diagnostics, performance optimization, and reliability features, working closely with hardware, validation, and system teams.

Key Responsibilities

Storage Firmware Development

• Design and implement embedded firmware for storage devices such as SSDs or storage controllers.
• Develop firmware modules for device initialization, command processing, and data movement.
• Implement and maintain state machines and control logic for reliable storage operation.
• Implement recovery mechanisms to ensure data integrity and device reliability.
• Optimize firmware for throughput, latency, and power efficiency.
• Analyze and improve performance under various workloads.
• Add robust error detection, logging, and recovery mechanisms.
• Develop low‑level drivers and hardware interfaces as required.
• Support firmware integration with host software and system drivers.
• Debug complex firmware and hardware interaction issues using JTAG, logs, traces, and emulation/simulation tools.
• Collaborate with validation teams to reproduce, analyze, and fix issues.
• Support bring‑up and stabilization on new platforms and silicon revisions.

We are looking for an Embedded Storage Firmware Engineer to design, develop, and maintain firmware for high performance storage devices and controllers. In this role, you will work close to the hardware, building reliable, high‑performance firmware that manages data movement, flash media, and device behavior under real‑world workloads.

You will contribute across the storage firmware stack, including boot, device initialization, data path, error handling, diagnostics, performance optimization, and reliability features, working closely with hardware, validation, and system teams.

Key Responsibilities

Storage Firmware Development

• Design and implement embedded firmware for storage devices such as SSDs or storage controllers.
• Develop firmware modules for device initialization, command processing, and data movement.
• Implement and maintain state machines and control logic for reliable storage operation.
• Implement recovery mechanisms to ensure data integrity and device reliability.
• Optimize firmware for throughput, latency, and power efficiency.
• Analyze and improve performance under various workloads.
• Add robust error detection, logging, and recovery mechanisms.
• Develop low‑level drivers and hardware interfaces as required.
• Support firmware integration with host software and system drivers.
• Debug complex firmware and hardware interaction issues using JTAG, logs, traces, and emulation/simulation tools.
• Collaborate with validation teams to reproduce, analyze, and fix issues.
• Support bring‑up and stabilization on new platforms and silicon revisions.

Looking for a 5+ years experienced Engineer with good understanding of Analog concepts, experience of from scratch design of key analog blocks, integrating smaller blocks to create functional I/Ps and full ownership of those, ICs and well versed with Transistor level design flow, to join the 2.6B$ Power Business Unit. The candidate will get to work on a wide range of exciting products such as PMICs, Linear and Switching DC-DC converters powering the next generation of most sought-after phones and hand held devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.

Essential Functions:

• Must be proficient in designing and owning key analog blocks including Bangdap references, Analog Buffers, Op-Amps, Comparators, High speed level shifters etc.
• Must be able to come up with architectures to meet block level performance specifications.
• Must be well versed of the standard architectures and be able to bring in innovative ideas to improve designs to meet challenging specifications.
• Should have clear understanding of analog layouts and should be able to work closely with and guide layout engineers to ensure quality layout to meet the desired performance.
• Must be conversant with the standard design, extraction and simulation flows & tools, speed, convergence, accuracy trade-offs and should be able to optimize setups based on Pre/Post (with/without) Parasitic using simulator options, debug and navigate through tool related challenges.
• Should be able to mentor Freshers and Junior engineers for upscaling their technical skills as well as other skills needed for better efficacy.
• Should be able to develop multiple blocks with minimal supervision, take full ownership to drive all aspects within committed schedule and work closely with Sr members of Design team to support them build subsystem/chip top.
• Experience of silicon validation and debug is a strong advantage.
• Should have good understanding of ESD and be able to design the I/O ring for the IC

We are seeking a Security Firmware Engineer to design, implement, and maintain security‑critical components in embedded firmware for next‑generation storage and controller products. This role focuses on device‑level security, including secure firmware update, lifecycle management, debug port control, Root of Trust (RoT) interactions, and protection of critical assets such as keys, OTP, and credentials.

The ideal candidate has strong low‑level firmware expertise combined with hands‑on experience in embedded security architectures and secure system design.

Key Responsibilities

Security Firmware Architecture & Development

• Design and implement security layers within device firmware, aligned with product security requirements and ASIC security IP capabilities
• Integrate firmware with Root of Trust (RoT) subsystems, including support for both hardware‑based and firmware‑based RoT models where applicable. 
• Ensure secure handling of cryptographic material and prevention of unauthorized access.
• Implement and integrate cryptographic primitives and related authentication and encryption flows used in firmware
• Work closely with hardware teams to leverage ASIC security IPs, HSMs, and secure key storage.
• Support security testing, threat analysis, and vulnerability mitigation during development and validation cycles.
• Participate in design reviews, security assessments, and risk evaluations.

We are looking for a Front‑End PCIe Firmware Engineer to design, develop, and maintain the device‑side PCIe Front‑End firmware stack for next‑generation high‑performance storage controllers. In this role, you will own key layers of the PCIe firmware responsible for link bring‑up, configuration space management, MMIO, interrupts, DMA, and command/queue handling, working closely with hardware, validation, and host‑software teams.

Key Responsibilities

• PCIe Front‑End Firmware Development

  • Design and implement firmware for PCIe initialization, link bring‑up, and configuration space programming (BARs, capabilities, MSI/MSI‑X).
  • Develop MMIO‑based control and status interfaces used by host software.
  • Work closely with DMA engines to enable high‑bandwidth, low‑latency host‑to‑device and device‑to‑host data transfers. 

• Architecture & Cross‑Functional Collaboration

  • Collaborate with hardware design teams on PCIe IP integration and bring‑up.
  • Partner with validation teams on FPGA, emulation, and ASIC debug.
  • Work with host‑side driver and system software teams to define clean, scalable interfaces. 

• Debugging & Performance Optimization

  • Debug complex system‑level issues spanning firmware, hardware, and host.
  • Profile and optimize PCIe throughput, latency, and interrupt efficiency.
  • Support bring‑up on pre‑silicon and post‑silicon platforms.

The Cloud Infrastructure Networking Engineer is responsible for designing and implementing the enterprise data architecture. This role will lead the development of scalable, secure, and integrated data platforms to support analytics, compliance, and business operations.

This role will be the cloud networking authority for the AWS environment. This role owns the design, operations, and reliability of everything from VPC architecture and firewall policy to remote access and infrastructure automation. This role also brings strong systems-engineering instincts: incident leadership, monitoring hygiene, and the drive to reduce operational toil over time.

This is a high-autonomy individual contributor role. This role sets direction for networking decisions, make the calls, and drive execution. This role will partner closely with Security and platform engineering, and own the networking domain

Responsibilities

AWS Cloud Networking

• Design and operate VPCs, subnets, routing, segmentation, ingress/egress patterns, security boundaries, and VPC endpoints/PrivateLink-style connectivity
• Define scalable networking standards that make workload onboarding consistent, secure, and repeatable
• Troubleshoot complex connectivity issues across AWS: routing, access controls, DNS resolution patterns

Palo Alto Firewalls & GlobalProtect

• Administer Palo Alto firewall policy lifecycle: safe changes, segmentation strategy, troubleshooting
• Own GlobalProtect remote access operations, stability, access controls, incident response
• Partner with Security to ensure network controls align with risk posture and audit expectations

Infrastructure as Code & Automation

• Build and maintain AWS networking and firewall infrastructure using Terraform (reusable modules, reviewable changes, controlled rollouts)
• Build and maintain GitHub Actions workflows for infrastructure CI/CD (plan/apply gating, workflow reliability)
• Automate operational tasks with Python and Bash (PowerShell is a plus)

Operational Excellence

• Support production infrastructure across Linux and Windows (patching, hardening, reliability improvements)
• Participate in on-call rotation and lead incident response for infrastructure and connectivity issues
• Improve monitoring, alerting, and operational visibility to catch issues earlier
• Drive root-cause analysis and prevention work to reduce repeat incidents

About the position:

As a Staff firmware verification engineer, you will be part of firmware verification team that design and develop white box and grey box tests in Python to verify SSD firmware designs for each firmware feature. This position is specifically to focus on verification and validation of SSD firmware features. You will be working closely with product architects and firmware engineers to create a comprehensive firmware verification test for SSD features. In this role, you will be contributing to test strategy, test development, integrating the tests using various development platforms, deploying it on firmware verification lab for regression runs and perform failure analysis. The role focuses on defining and executing robust firmware verification strategies for PCIe, MMIO, DMA, and custom host–device protocols across both pre‑silicon and post‑silicon environments.

Responsibilities:

• Collaborate closely with firmware engineers & architects on product architecture and designs to define the comprehensive verification plan to validate each SSD features
• Design, Develop and Integrate the white box and gray box tests on SSD products in roadmap
• Conduct test plan reviews and code reviews to ensure the tests are scalable and meeting the requirements
• Participate in driving failure analysis and collaborate with integration/execution engineers for test deployment.
• Validate designs against PCI Express Base Specification (up to Gen5/Gen6), ensuring compliance with electrical, logical, and transaction-layer requirements.
• Define and own firmware validation strategy for PCIe front-end subsystems, including MMIO address spaces, BARs, resets, interrupts, and error handling.
• Define, plan, and execute system-level validation strategies for PCIe front-end (PHY + controller) IP and SoC-level integration.
• Integrate tests into scalable automation frameworks supporting simulation, emulation, and silicon validation.
• Debug firmware issues, perform front-end error injection, and expose design or integration defects.
• Validate PCIe compliance, MMIO access integrity, and robustness of fault detection and recovery mechanisms.
• Review and verify firmware trace logs and debug telemetry for correctness and completeness.
• Drive validation readiness across pre‑silicon and post‑silicon platforms, ensuring alignment of firmware specs, drivers, and test collateral.
• Interface with cross‑functional stakeholders to ensure validation coverage meets product and customer requirements.
• Drive compliance and interoperability testing with various endpoint/root-complex devices, switches, and add-in cards.