Total 6 job vacancies by Brightecs Innovation Pte. Ltd.

Key Responsibilities:

• Responsible for the architecture design, RTL encoding (Verilog/SystemVerilog), and functional verification of digital control logic in 3D-NAND memory;
• Design a state machine (FSM) to manage complex NAND operation processes (such as Program, Read, Erase, Copy-back, Suspend/Resume, etc.);
• Develop a command decoder and address/parameter parsing logic to ensure compliance with JEDEC and internal specifications;
• Implement high-precision timing control logic to accurately generate the internal timing signals required for various operations (such as tR, tPROG, tBERS, etc.);
• Deeply involved in the physical layer and link layer logic implementation of ONFI (Open NAND Flash Interface) or Toggle Mode interface protocols, supporting DDR, NV-DDR, NV-LPDDR, and other modes;
• Collaborate with the analog/mixed-signal team to define array access timing, voltage switching windows, and read/write path control interfaces;
• Collaborate with firmware (FW) and system architecture teams to develop register maps, interrupt mechanisms, error handling strategies, and debug interfaces;
• Support UVM verification environment setup, provide Design for Testability (DFT) support, and participate in FPGA prototyping;
• Participate in chip bring-up, post-silicon debugging, and performance optimization to ensure products meet specification requirements.

Required Qualifications:

1. Education: Master's degree or above
2. Major: Microelectronics and Integrated Circuits, Electrical Engineering, Computer Engineering, or related fields;
3. Other Requirements:

• Minimum 5 years digital IC design experience, experience in NAND Flash or SSD controller projects is a plus;
• In-depth understanding of ONFI 4.x or Toggle 2.0/3.0 protocol specifications, with practical interface IP development or integration experience;
• Experience in control logic design under 3D-NAND or TLC/QLC architectures is a plus;
• Familiar with ECC control interfaces (such as LDPC/BCH engine scheduling and interaction);
• Excellent cross-functional collaboration skills, able to communicate efficiently with simulation, firmware, verification, testing, and product teams to jointly develop technical solutions.
• Experience with successfully tape-out and mass-produced memory chip projects is a plus.

Key Responsibilities:

• Lead the architecture design (e.g. memory cells, select transistors, and peripheral devices), process integration, electrical characterization, modeling and simulation, failure analysis for 3D NAND devices.
• Design and execute DoE, analyze the impact of process variations on device performance and reliability (such as durability and data retention), and propose improvement solutions.
• Collaborate with the process development team to assess new device architectures, driving technology iteration.
• Write detailed technical reports and support customers or internal teams in resolving related technical issues.

Required Qualifications:

1. Education: Master's degree or above
2. Major: Microelectronics, physics, material science & engineering, chemistry;
3. Other Requirements:

• 8+ years of semiconductor device work experience, 3+ years of 3D NAND work experience.
• In-depth knowledge of 3D NAND device physics, familiar with its principles, failure modes, and reliability mechanisms.
• Troubleshooting, and problem-solving capabilities, with experience in successfully improving device performance or yield.
• Familiar with advanced semiconductor manufacturing processes and integration flows.
• Strong cross-team communication and collaboration skills.

Key Responsibilities:

• Responsible for the circuit design, simulation, and verification of key analog/mixed-signal modules for 3D-NAND memory, including but not limited to: 1) Row/Column Decoder design and optimization. 2) Charge PUMP architecture design to meet multi-voltage domain, high efficiency, and low noise requirements. 3) Sense Amplifier circuit development, balancing speed, power consumption, and read accuracy. 4) High-voltage switch (HV Switch) and level shifter design to support >20V high-voltage operation. 5) I/O interface circuitry (including ESD protection, drive capability matching, and signal integrity optimization).
• Establish and maintain Verilog-A behavioral models of key modules for rapid system-level simulation and verification;
• Perform array-level mixed-mode simulation, proficient in using tools such as SPICE, Spectre, and HSPICE, and combining Verilog/Verilog-AMS for large-scale circuit verification;
• Collaborate closely with the device team to optimize circuit performance and reliability based on actual device characteristics (e.g., Fowler-Nordheim Tunneling, Band-to-Band Tunneling);
• Participate in the implementation of ECC (Error Correction Code) schemes, understanding the impact of encoding mechanisms such as BCH/LDPC on read/write circuits;
• Support the layout team in completing high-voltage circuit layout, ensuring compliance with DRC/LVS rules and high-voltage isolation requirements (e.g., NBL, Deep Nwell);
• Analyze and resolve analog circuit-related failures encountered in mass production, improving product yield and reliability.

Required Qualifications:

1. Education: Master's degree or above
2. Major: Microelectronics and Integrated Circuits, Semiconductor Devices, or related fields;
3. Other Requirements:

• 5+ years of experience in analog/mixed-signal circuit design, and experience in NAND Flash or other non-volatile memory (NVM) is a plus ;
• Proficient in SPICE-type simulation tools (such as HSPICE, Spectre) and Verilog/Verilog-AMS, with experience in array-level large-scale mixed-signal simulation;
• Proficient in Verilog-A modeling, able to build accurate and efficient analog behavior models;
• Solid knowledge in analog/digital circuit design, able to independently solve physical and circuit technical challenges in NAND design;
• Excellent cross-team collaboration skills, able to communicate effectively with device, process, digital, verification, and testing teams.

Key Responsibilities:

• Responsible for the performance, power consumption, and reliability testing and analysis of NAND memory products, and formulating test specifications and verification processes.
• Develop and maintain test equipment (ATE), including the definition and implementation of test modes such as BIST, DFT, and DFM, continuously improving test coverage and optimizing test time.
• Locate the causes of product failures after delivery and at the wafer stage through electrical failure analysis, design circuit analysis, physical failure analysis, and data analysis.
• Collaborate with the product design team and process team to identify the root causes of failures and drive the implementation of solutions.
• Support the testing and debugging of products in system-level applications (such as SSD, UFS, eMCP) to ensure efficient use by customers and the system side.
• Complete user manual verification, product test function verification, and participate in other test-related tasks assigned by the supervisor.

Required Qualifications:

1. Education and major: Master's degree or above in microelectronics, integrated circuits, electronic engineering, computer science, automation, physics, materials science, or other related STEM fields.

2. Experience requirements:

• Familiar with semiconductor product principles and testing mechanisms; background in memory (NOR/NAND Flash, SRAM, DRAM, phase-change memory, ferroelectric, etc.) testing or design verification is a plus.
• Experience in testing 3D-NAND, TLC/QLC, or flash memory products is a plus.
• Experience with successfully tape-out and mass-produced memory chip projects is a plus.

3. Technical skills:

• Proficient in C/C++, Python, Perl, etc., and familiar with UNIX/Linux environments.
• Experience in ATE (Automatic Test Equipment) development (e.g., T5830, T5833, Magnum V93K, etc.).
• Familiar with the functions, performance, and reliability indicators of memory products.
• Familiar with design-for-test (CFT), DFM, and other design-for-test (CFT) methodologies.

4. Other skills:

• Strong logical analysis, learning, and problem-solving abilities.
• Good communication, organizational, and teamwork skills.
• Proactive, steady, meticulous, responsible, and able to work under pressure.

Key Responsibilities:

• Define the overall 3D-NAND memory architecture, including array organization (Plane/Bank/Page/Block structure), word line/bit line layout, shared resource strategies, etc.
• Lead architecture feasibility studies, technical risk assessments, and roadmap planning, promoting IP reuse, scalability design, and future technology node evolution.
• Design and optimize erase/read algorithms, balancing speed, endurance, data retention, and interference management (such as read disturbances and program disturbances).
• Develop ECC (Error Correction Code) strategies and integration solutions, evaluating the impact of BCH, LDPC (hardware decoding/software decoding), and other solutions on area, latency, power consumption, and error correction capabilities.
• Define page and block management level logic, supporting advanced functions such as copy-back, multi-plane operation, suspend/resume, and background erase.
• Manage the balance of performance (throughput/latency), area (die size), power consumption (active/standby power), and reliability (P/E cycles, data retention) to support product positioning (consumer/enterprise/automotive grade);
• Collaborate closely with device/process teams to optimize circuit and algorithm designs based on actual 3D stacked structures (such as CT/FG charge trapping, vertical channels, word line stacking layers);
• Participate in the selection and customization of ONFI/Toggle Mode interface protocols, defining register mappings, command set extensions, and low-power modes;
• Coordinate cross-team (circuit, device, testing, product) technical reviews, and formulate architecture design specifications and simulation verification standards;
• Support post-silicon verification, yield analysis, and customer problem-solving, optimizing architecture design in a closed-loop manner.

Required Qualifications:

1. Education: Master's degree or above (PhD preferred) in Microelectronics and Integrated Circuits, Electrical Engineering, Computer Engineering, or related fields.
2. Other Requirements:

• 8+ years of Flash memory development experience, including at least 5 years as architecture or key technology lead;
• Proficient in 3D-NAND physical structure and operation mechanisms, with in-depth understanding of charge trapping (CT) or floating gate (FG) technologies, vertical channel, word line stacking, crosstalk, and other characteristics;
• Familiar with TLC/QLC/PLC multi-bit memory mechanisms and their challenges to read/write algorithms, ECC, and wear leveling;
• Familiar with mainstream interface protocols such as ONFI 4.x / Toggle 3.0;
• Excellent systems thinking and cross-domain integration capabilities, able to efficiently coordinate circuit, device, firmware, verification, testing, and product teams;
• Excellent technical documentation writing and technical decision-making communication skills;
• Ability to track cutting-edge industry technologies (such as HBM-NAND hybrid storage and in-memory computing architecture) and drive architectural innovation and patent portfolio development;
• Complete NAND architecture delivery experience, successfully mass-produced 64-layer or higher 3D-NAND products is a plus;
• In-depth understanding of the ECC architecture (BCH/LDPC) and NAND controller collaboration mechanism is preferred;
• Familiarity with the impact of reliability modeling under advanced processes (such as TDDB, HCI, RTN) on the architecture;
• Publication of NAND-related papers at international conferences (such as ISSCC, VLSI, IMW) is a plus.

Key Responsibilities:

1. Si-based 3D DRAM:

1) Novel Metals & Interconnect Strategy:

• Lead the research and integration of advanced low-resistivity conductive materials for sub-10nm metal line and interconnect applications.
• Focus on materials screening, physical property optimization (e.g. thermal stability and work function engineering), process optimization, and HVM readiness evaluation and preparation.

2) Advanced Junction Formation:

• Define the process for ultra-scaled junction formation.
• Develop low-thermal-budget process and technology to achieve precise doping profiles and activation, ensuring optimal device performance in HAR 3D structures.
• Develop novel characterization technologies for precise junction profile measurements in complex 3D structures.

3) 3D Architecture & Silicide Integration:

• Overcome challenges in high aspect ratio structures.
• Develop robust n-type silicide processes for complex 3D geometries, ensuring low contact/barrier resistance, high step coverage, high thermal stability, and future scalability in deep trench/via applications.

2. DRAM with novel channel oxide materials:

• Development of novel DRAM array memory architecture.
• Research and development of novel DRAM transistor channel materials.
• Novel device design and performance optimization.
• Research and development of key processes and process integration technologies.
• Development of TEG design, peripheral circuit design, and structural/electrical testing solutions.
• Materials, process, and device simulation.

Required Qualifications:

1. Education: Master's degree or above (PhD preferred).
2. Major: Physics, material science & engineering, chemistry.
3. Other Requirements:

• 8+ years of DRAM memory development experience, including at least 5 years as architecture or key technology lead.
• Familiar with TLC/QLC/PLC multi-bit memory mechanisms and their challenges to read/write algorithms, ECC, and wear leveling.
• Excellent systems thinking and cross-domain integration capabilities, able to efficiently coordinate circuit, device, firmware, verification, testing, and product teams.
• Excellent technical documentation writing and technical decision-making communication skills.
• In-depth understanding of the ECC architecture (BCH/LDPC) and DRAM controller collaboration mechanism is preferred.
• Familiarity with the impact of reliability modeling under advanced processes (such as TDDB, HCI, RTN) on the architecture.
• Publication of DRAM-related papers at international conferences (such as ISSCC, VLSI, IMW) is a plus.