Total 406 operations engineer job vacancies in Manufacturing / Production category in Singapore

THE ROLE: 

As a Senior Engineer, you will collaborate with various Product Development Groups. This individual serves as a critical technical point of contact to the business, design, platform validation and product engineering teams. We have competitive benefit packages and an award-winning culture. Join us!  

THE PERSON: 

A successful candidate is one who can drive technical decisions independently, has accountability for accuracy, reliability and completeness of assignment results critical to the project’s success. This role allows the opportunity to influence technical decisions that have a significant impact on multiple products or the product line.  

KEY RESPONSIBILITIES: 

• Ensures high uptime, ensures preventive maintenance (PM) execution, and seamless vendor coordination for resolving tools hardware and software issues. Primary advanced toolset coverage: Focused Ion Beam, Reactive Ion etchers, Nano‑probers, Scanning electron microscopes and Transmission electron microscopes 
• The role partners closely with equipment owners, lab operations, EHS, and external OEMs to sustain capability, drive MTBF/MTTR improvements, and enable rapid turns on high‑priority cases.
• Design new lab space with strict environmental control involving vibration, EMI and acoustics.
• Lead structured troubleshooting and root‑cause eradication (5‑Why, Ishikawa, FMEA); convert escapes into standard work and documented fixes
• Serve as single point of contact for OEMs and third‑party service providers; coordinate field service, escalations, and remote diagnostics
• Manage service contracts, PM bundles, and time‑and‑materials events; negotiate scope vs. cost; track vendor KPI adherence and corrective actions
• Enforce LOTO, ESD, chemical/gas handling, UHV safety, and radiation/beam compliance as applicable
• Partner with FA engineers on readiness gates for new methods/fixtures; support tool installation, lab moves, and capability upgrades
• Provide on‑call/shift coverage as needed for bring‑up, critical debug, and factory‑stop events

PREFERRED EXPERIENCE: 

• Hands on maintenance experience with complex capital equipment involving vacuum systems, motion/servo control, pneumatics, high voltage, and embedded SW/FW
• Demonstrated ability in systematic troubleshooting, reading electrical/pneumatic schematics, and using diagnostic tools (oscilloscope, DMM, leak detector, RGA)
• Effective communication with vendors and cross site teams; ability to coordinate multi party interventions under time pressure
• Experience in failure analysis tools, including alignments, stage/probe calibration, column health, and detector
• Knowledge of UHV, turbo/cryogenic pumps, gas handling, plasma sources, beam columns, and vibration/thermal isolation
• Lab‑based role with occasional off‑shift or weekend coverage during critical events and planned PMs
• Some travel for OEM training, factory repair, or acceptance tests may be required

ACADEMIC CREDENTIALS: 

• Bachelor’s degree in Mechatronics Engineering (or Mechanical/Electrical with mechatronics focus)

• Provide support for operational and technical activities
• Machine & Equipment maintenance / calibration
• Establish SOP and machine manual to provide comprehensive servicing and maintenance programmes
• Identify areas of process improvement and automation to implement work improvement programmes to achieve desired machine efficiency and reject rate
• Plan, evaluate and improve technical/engineering projects for cost and productivity
• Implementation of industrial safety practice to ensure compliance
• Any other ad-hoc tasks as assigned

JOB REQUIREMENTS:

• Min Degree in Mechanical / Electrical Engineering or related discipline
• No experience needed, training provided

Office hours, Mon to Fi
Medical Device MNC

Interested candidates, please forward your resume to kevynhuang@recruitexpress.com.sg

Consultant: Huang Jingsheng Kevyn (R1333338)
Recruit Express Pte Ltd (99C4599)

SSMC (Systems on Silicon Manufacturing Company Pte. Ltd.) is a Joint Venture between NXP and TSMC. We offer flexible and cost-effective semiconductor fabrication solutions by maintaining fully equipped SMIF cleanroom environment, 100% equipment automation and proven wafer-manufacturing processes.

We're looking for innovative, passionate, and talented people like you to join our team.

We’re searching for an Engineer/ Senior Engineer to be part of our Product Engineering Department diverse team of talent.

What you will be working on:

• Ensuring 1st time yielding silicon, benchmark D0 for baseline and products.
• Identify & resolve Product, Test & Fab-Process related yield limiters in shortest time possible.
• Technical interface with Business Lines/customers
• Driver for yield improvement
• Resolve product yield, quality and reliability issues
• Perform pre-tapeout risk assessment and communicate with Business line/Fab on the necessary actions to eliminate/minimize the risk.
• Work with Customers/Mother Fab on the DfM related issue.
• Conduct product yield analyses to identify root cause of wafer sort and final test failures
• Set up fault diagnostic capabilities for yield improvement
• Work with Business line/customers on product low yield disposition
• Perform electrical and physical failure analysis to isolate fail location
• Drive the yield improvement task force

More about you:

• Master/bachelor’s degree in electrical / Electronic Engineering or Science in Physics
• 2 – 8 years product and/or test engineering, failure analysis or process-integration experience
• Experience in Fab process, yield engineering or design will be an added advantage
• In depth knowledge of semiconductor device physics, electrical & electronics engineering fundamentals & wafer fabrication processes
• Strong analytical & problem-solving skills
• Good interpersonal and communication skills

SSMC is firmly committed to upholding equal employment opportunities for all individuals. We strictly adhere to the Tripartite Guidelines on Fair Employment Practices (TGFEP), the Singapore Food Safety and Security Act 2025 (FSSA 2025), and the Singapore Code of Advertising Practice. All qualified applicants will receive non-discriminatory consideration for employment on the basis of merit and regardless of age, race, gender, religion, marital status and family responsibilities, or disability, or any other attributes as protected by the relevant laws.

Role Overview

We are looking for a hands-on Senior DevSecOps & Cloud Architect to help design, implement, and standardize a modern application platform based on Angular frontend and .NET (C#) backend on AWS Cloud.

This role will play a critical leadership position in defining best practices for application architecture, security, CI/CD pipelines, and cloud infrastructure, enabling scalable and secure delivery across teams.

Key Responsibilities

• Define reference architecture for Angular + .NET applications on AWS
• Lead implementation of DevSecOps practices (SAST, DAST, SCA, secure SDLC)
• Design and build end-to-end CI/CD pipelines (build, test, deploy automation)
• Establish cloud architecture standards (EKS/ECS, API Gateway, RDS, S3, VPC)
• Implement Infrastructure as Code (Terraform / CloudFormation)
• Create reusable templates, pipelines, and frameworks
• Drive security, scalability, and reliability across applications
• Enable development teams with best practices and tooling

Required Skills

• Strong experience in:
  • .NET / C# (ASP.NET Core)
  • Angular frontend architecture
• Deep expertise in:
  • DevSecOps & CI/CD tools (GitHub Actions, GitLab CI, Azure DevOps, Jenkins)
  • AWS Cloud services & architecture
• Hands-on with:
  • Docker, Kubernetes (EKS preferred)
  • Infrastructure as Code (Terraform preferred)
• Security knowledge:
  • SAST / DAST / SCA tools
  • API security (OAuth2, JWT)
  • Secrets management

Nice to Have

• Experience in platform engineering / internal developer platforms
• Observability tools (CloudWatch, Prometheus, Grafana)
• AWS Certifications (Solutions Architect / DevOps)
• Background in legacy modernization (e.g., PHP / VB.net to cloud-native)

What Success Looks Like (6 Months)

• Defined and implemented standard architecture blueprint
• Delivered secure, automated CI/CD pipelines
• Established DevSecOps baseline practices
• Built reusable templates and frameworks for developers
• Improved deployment speed, system reliability, and security posture

Ideal Candidate

• Strong balance of hands-on engineering and architecture leadership
• Experience building or standardizing platforms from the ground up
• Ability to influence, guide, and drive adoption across engineering teams

Job Summary:
Coherent is currently hiring a Senior Manufacturing Engineer to work at our manufacturing site located in Singapore. We are looking for a hands-on candidate for our industry-leading laser technology products. The Manufacturing Engineer will be responsible for developing, optimizing, and maintaining the manufacturing processes used in the production of laser systems and optical assemblies. This role ensures high-yield, cost-effective, and reliable production through continuous process improvement, equipment qualification, and close collaboration with design, quality, and supply chain teams. The engineer will be a key technical link between R&D and production, focusing on scalability, manufacturability, and operational excellence.

Primary Duties & Responsibilities

1. Process Development and Optimization

• Develop, document, and implement manufacturing processes for laser modules, optical assemblies, and related sub-systems.
• Define critical process parameters for optical alignment, bonding, soldering, and laser cavity assembly.
• Conduct DOE (Design of Experiments) and SPC (Statistical Process Control) to optimize yield and minimize process variability.
• Translate R&D prototypes into robust, repeatable production processes.

2. Production Support

• Provide hands-on technical support to production teams for troubleshooting yield issues, process deviations, and equipment downtime.
• Implement root cause analysis and corrective actions for production failures (using tools like DMAIC, FMEA, Ishikawa).
• Support daily manufacturing operations to meet production schedules and performance targets (throughput, yield, quality).

3. Equipment and Tooling Management

• Specify, qualify, and maintain production equipment such as optical benches, alignment stations, bonding systems, and test setups.
• Design and procure custom fixtures, jigs, and alignment tools to improve precision and throughput.
• Ensure calibration and preventive maintenance of manufacturing and metrology tools.

4. Quality and Continuous Improvement

• Work with Quality and Reliability teams to ensure process compliance to ISO 9001 / ISO 13485 standards.
• Develop and update process documentation: work instructions
• Drive Lean and Six Sigma initiatives for process improvement, waste reduction, and cost optimization.

5. Cross-Functional Collaboration

• Interface with Design Engineering for Design for Manufacturability (DFM) reviews and prototype builds.
• Collaborate with Supply Chain and Vendors to ensure component quality and manufacturability.
• Support NPI (New Product Introduction) transitions from R&D to production.

6. Data Analysis and Reporting

• Collect and analyze process data to identify trends and improvement opportunities.
• Implement real-time data collection and traceability systems (MES, SPC dashboards).
• Present yield, performance, and process capability metrics to management.

Education & Experience

• A bachelor’s or master’s degree in engineering or its equivalents with at least 3-5 years of relevant work experience in Photonics or a related manufacturing field
• Possess technical expertise pertaining to Manufacturing, Assembly & Test Processes for mechanical assemblies, PCBA and optical components.
• Strong problem-solving skills and excellent knowledge in Six Sigma DMAIC approach, Lean principles, DOE, SPC, FMEA, GR&R and other quality improvement tools. Certified Six Sigma Green or Black Belt will be an advantage.
• Excellent interpersonal skills with good verbal and written communication skills.
• Self-directed and able to work independently with little or no direct supervision.
   

JOB SUMMARY

The Engineer will support the Engineering Department in planning, designing, implementing and managing; integrated, production and service delivery systems that assure performance, reliability, maintainability, schedule adherence and cost control within the production site.

Main focus: conducts studies to determine the most efficient sequence of operations and workflow and recommends methods for maximum utilization of production equipment and personnel.

ESSENTIAL DUTIES AND RESPONSIBILITIES

· Monitor and continuously improve daily quality/efficiency performance for assigned areas.

· Design and procure production tooling, processing equipment and workstations.

· Coordinate layout and workstation move activities.

· Prepares time estimates for proposed projects and evaluates time factors.

· Minimize change over time by ensuring programs use common set-ups where possible.

· Verify that machine maintenance is being performed on schedule.

· Reduce machine-generated scrap by monitoring machine management data and taking corrective action to improve or correct the operations.

· Reduce manual assembly scrap by monitoring quality data and taking corrective action to improve or correct the operations.

· Analyzes work force utilization, facility layout, and operational data such as production costs, process flow charts, and production schedules, to determine efficient utilization of workers and equipment.

· Adhere to all safety and health rules and regulations associated with this position and as directed by supervisor.

· Comply and follow all procedures within the company security policy.

· May perform other duties and responsibilities as assigned.

JOB QUALIFICATIONS

EDUCATION AND KNOWLEDGE REQUIREMENTS

· Bachelors Degree in Mechanical or Manufacturing from four-year college or university preferred; or related experience and/or training; or equivalent combination of education and experience.

· Preferably 3 years of relevant working experience but fresh graduate is also encouraged to apply.

· Key Requirements:

o Understanding and application of broad range of industrial engineering tools (ie. Work measurement, process mapping, facilities and workstation design, etc.)

o Understanding of Jabil’s global strategies and direction

o Understanding of site’s facilities, capabilities and how they tie back to the Jabil strategies and direction

o Strong analytical ability

o Able to implement continuous improvements and cost reduction programs

o Good communication skills

· Proficiency in use of personal computers, Microsoft Office products, Microsoft Visio, Microsoft Project, and AutoCAD skills required.

THE ROLE:

Returns Debug and RMA execution in Quality & Reliability organization, provide supportive functions to the organization to ensure customer quality issue being addressed evoking the required actions via failure analysis to improve product quality.

THE PERSON:

You will also need to possess strong verbal and written communication skills which are essential when working with a global team. A proactive, outstanding teammate who focuses on teamwork, team building, and growing team success.

AMD's environment is fast paced, results oriented and built upon a legion of forward-thinking people with a passion for winning technology!

KEY RESPONSIBILITIES:

• Perform analysis & report writing on customer returns electrical FA, include analysis on Automated Test Equipment (ATE) and System Level Test (SLT), duplicate customer reported failure on Platform level and perform board level debug.
• Customer returns debug covering pre & post Mass Production, field return including Excursion/Critical issue, also cover debug for Defect Part Per Million (DPPM) improvement.
• Drive cross-functional collaboration by proactively engaging with Device Analysis and Product Engineering teams to lead fault isolation and root-cause investigations.
• Identify and define test coverage enhancements that strengthen product quality, prevent customer-facing failures, and support long-term reliability improvements.
• Provide technical direction in diagnosing complex issues, influencing validation strategies, and ensuring findings translate into actionable quality improvements across functions.
• Provide conclusive and convincing results and align with Program/PLQ/Customer Interfacing team on final analysis report writing for customer communication.
• Local product ownership roles that include but not limited to understanding, tracking and releases of ATE/SLT/OSV which covers RMA/OSV program, test program contents, and Go-To person on owned product technical queries.
• Role model as a coach for internal team that able to guide junior on technical challenges that arise during work for specific IP or failure category.
• Other duties as assigned by supervisor.

PREFERRED EXPERIENCE:

• Strong in silicon debug or Failure Analysis knowledge either on electronics system level or Integrated Chip.
• Candidate should be analytical and detail oriented, strongly interested in debugging complex system, self-starter, and fast learner
• Experience working in root causes digital or analog failure or SCAN/MBIST/High Speed Loopback failure.
• GPU, CPU or x86 architecture knowledge is much preferred
• Java, Python, Perl coding or Linux Shell scripting skills
• Window and Linux proficiency.
• JTAG knowledge is a plus.
• Knowledge in ATE test class/method experience with Advantest 93k platform is a plus.
• Experience in computing hardware, PC systems or Server platform projects or task is a plus.
• Knowledge or experience in PCB board or Customer Reference Board platform (schematics, layout, hardware configuration/setup, platform validation) is a plus
• Knowledge in industry standards like PCIE, USB, or high bandwidth memory is a strong plus
• Experience in AI or Machine Learning project or task is a plus. 

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in Electrical/Electronic Engineering or Computer Engineering

Job Overview

Major Responsibilities: Engineer will be responsible for characterization and developing cost-effective manufacturing test solution for leading‑edge Qualcomm SoC products using advanced ATE platforms. Engineer will be developing Characterization and Test Plans, test hardware requirement documents, ATE tests/routines/programs to execute test plans, driving first silicon debug to qualify designs fabricated at external foundries, performing technical data analysis of parametric performance, driving failure analysis to completion, analyzing high volume manufacturing yields and driving test time reduction, and innovating on new test solution. Engineer will be working with IC design, system engineering, DFT/DV engineering, and Hardware applications engineering in a time critical environment across the globe. The individual selected for the position, needs to be proactive, able to work in a fast-paced dynamic environment independently, and committed on delivering quality work.

Minimum Qualifications

Bachelor's degree (or higher) in Engineering, Information Systems, Computer Science, or related field. At least 8+ years of related work experience.

Preferred Qualifications

- 3-8+ years of Test Engineering or related work experience.

- 1+ year in a technical leadership role with or without direct reports.

- Strong and hands-on ATE knowledge (Advantest 93K ATE is preferred).

- Experience in developing ATE SOC program from NPI stage to volume ramp stage and driving yield and test time reduction.

- Solid understanding in semiconductor Structural (Scan and Memory BIST) and functional testing. Good understanding of eletronics engineering fundamental. Basic knowledge on CPU, DSP, GPU will be a plus.

- Experience in one or more chiplet‑based or multi‑die products, including die‑to‑die (D2D) interfaces and associated test and yield challenges is a plus

- Knowledge and hands on experience with statistical analysis software package and techniques, quality and reliability testing.

- Experience in using collaboration tools such as GIT, SVN and JIRA.

- Strong software skills (Java, C/C++, Visual Basic, Perl, Python etc.) for programming and debugging test codes.

- Strong verbal and written communications skills. Able to organize effectively and document work thoroughly while working with local and remote teams. Has a moderate amount of influence over key organizational decisions.

Educational Requirements

Required: Bachelor's, Electrical Engineering or equivalent experience Preferred: Master's, Electrical Engineering or equivalent experience

THE ROLE:

We are the high-end test engineering team providing test solutions for Data Center New Product Introduction (NPI) under the Product Engineering Organization. We do exciting product development for leading-edge technology that will power the next generation processors used for high performance computing, data centers, and enterprise servers.

If you are looking for a fulfilling and challenging career as an engineer leading SLT (System Level Test) Thermal and Board SME (Subject Matter Expert), you are at the right place! As a MTS System Level Technical Lead, you will be responsible for defining, driving and enabling SLT test solution to meet NPI business milestones and KPI (test time, yield, cost, quality .The expectation is to perform leadership to have interaction with Silicon/Board/Power design teams, Product & Test Engineering teams, Customer Quality teams, software & platform teams to ramp GPU coverage with aggressive schedule while debug GPU fallout to ensure high yield. You will experience working with and learning from AMD’s talented engineering teams around the world.

THE PERSON:

We are looking for someone with strong technical, analytical, leadership and problem-solving skills, as well as demonstrating the characteristic of an independent and resourceful individual.

You will be proficient in your understanding about PCB Board and High Power Delivery (above 1kW) design methodology, Thermal dissipation as well as a broad understanding of various industry standards in OCP (Open Compute Project), such as JEDEC HBM3/4, PCIe, I2C/I3C, UEC (Ultra Ethernet Consortium) and UCIe (Unified Chiplet Interconnect Express) etc.

KEY RESPONSIBILITIES:

• Accountable to provide leadership to meet business milestone, cost and quality in GPU system level test area.
• Collaborate with internal teams to drive SLT board and power swim lane from pre-silicon, ASIC initial bring up to HVM (High Volume Manufacturing)
• Conduct engineering evaluations and analysis to drive closure of GPU production issues, qualify cutting-edge high power SLT thermal system for HVM
• Profile or characterize PI (Power Integrity), voltage droop, or power delivery issue observed on SLT platforms in collaboration with board/silicon designers
• Involves collaboration on or assuming the consultative or leadership responsibilities for a specific project or for product development initiatives
• May provide technical supervision or mentoring junior engineers
• Upscale overall team capabilities on low level system debug for AMD data center product families

PREFERRED EXPERIENCE:

• Experience and with good understanding of PCB board and Power Delivery design for high power GPU product (above 1kW), and board lifecycle from Eval to HVM (High Volume Manufacturing)
• Strong expertise with using analyzers and oscilloscopes, and other debug tools
• Knowledge and working experience on GPU and HBM architecture, SoC design and SoC power management features are a strong plus
• Strong and effective presentation, written and verbal communication skills, and the ability to work with geographically distributed product engineering teams
• Proficiency in Windows, and Linux operating systems
• Basic scripting proficiency for automation (Shell script, Perl, Ruby, Python)

ACADEMIC CREDENTIALS:

• BS/MS Electrical Engineering, Computer Engineering, or comparable disciplines

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.
  

  Performs hardware, software, semiconductor design or telecomm engineering assignments. This job mapping should be used only if the position cannot be mapped specifically to other design/development engineering jobs.

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.

Job Summary

The Production Engineer supports and optimizes daily electroplating operations to ensure consistent product quality, efficient production flow, and compliance with safety and environmental standards. The role requires strong knowledge of plating processes, chemical bath control, equipment maintenance, and continuous improvement.

Key Responsibilities

1. Process Parameter Control

• Perform daily checks on all process parameters (temperature, pH, current, bath levels, flow, pump condition).

• Audit operators to ensure each process step is carried out according to specification and SOP.

• Train operators on proper equipment usage: valve operation, pump priming and air-trap checks, chiller operation, and basic line troubleshooting.

• Ensure timely correction actions when deviations are found.

2. Process Optimization

• Identify opportunities to improve loading efficiency (fixture design, part orientation, racking method).

• Work with Production and Process Engineering to increase throughput and reduce bottlenecks.

• Support improvements on cycle time, workflow, and chemical usage.

3. Quality Troubleshooting

• Participate in root-cause investigations for defects (e.g., poor adhesion, uneven colour, stains, white spots, roughness).

• Work closely with QA to verify findings and implement corrective actions.

• Escalate complex technical issues to senior Process Engineers when deeper subject expertise is required.

4. Equipment & Line Readiness

• Support preventive maintenance activities for pumps, agitators, rectifiers, chillers, filtration systems, and plating/anodizing tanks.

• Assist maintenance team in diagnosing equipment abnormalities that affect production stability.

• Ensure calibration of basic instruments (pH meter, conductivity, thickness gauges) is done on time.

5. Documentation & Reporting

• Complete production forms, bath check sheets, process logs, and operator audit records accurately.

• Update SOPs and work instructions when process changes occur.

• Prepare daily reports on process status, defects, and deviations.

6. Safety & Environmental Compliance

• Ensure safe handling of parts, chemicals, jigs, and equipment.

• Follow SDS and internal EHS requirements for chemical storage and disposal.

• Support EHS team during inspections (wastewater, ventilation, PPE compliance).

• Conduct on-the-job safety briefings for operators.

Qualifications

• Degree or Diploma in Chemical Engineering, Mechanical Engineering, Materials Engineering, or related field.

• 1–5 years’ experience in plating/electroplating, surface finishing, or chemical processing preferred.

• Strong analytical, troubleshooting, and process improvement skills.

• Knowledge of Lean Manufacturing, SPC, and chemical safety standards.

Skills Required

• Understanding of electroplating techniques (e.g., nickel, chrome, zinc, gold, tin).

• Ability to read technical drawings and interpret plating thickness requirements.

• Experience with rectifiers, chemical pumps, dosing systems, and wastewater treatment.

• Good teamwork, communication, and leadership skills.

Job Description

• Industry/ Organization Type: Manufacturing
• Position Title: Manufacturing Engineer
• Working Location: Tai Seng
• Working Hours: 5 days (Mon – Fri, 8.00am – 5.30pm)
• Salary Package: Basic salary up to $4,500 + AWS + Performance Bonus
• Duration: Permanent Role

Key Responsibilities

• Assist in New Production Introduction criteria for the following: manufacturing process development, tool design, integrated schedules, design to cost, sourcing technical support, quality qualifications, test support, product cost out and, introduction into the supply chain.
• Provide technical leadership for manufacturing processes of cables, harnesses, electro-mechanical assemblies, inspection, testing, tool and fixture designs.
• Apply knowledge of electrical/ electronic equipment production and test methodologies.
• Help to manage effectively multiple priorities under tight deadlines and bring assigned projects/programs to successful completion and profitability.
• Gather data and develop manufacturing solutions and documentation required for supporting OMS, WI, Schematic, drawings, and specs.
• Perform assembly work and provide guidance to technicians/operators.
• Perform customers’ onsite support for repairs and rework related to assembly process and any other technical issue.
• Manage daily activities of the manufacturing function including BOM, Work Instructions, Engineering Change Order (ECO) and ERP System.
• Perform and support any assembly process during First Article & production stage to meet customer needs.

APPLY NOW!!!

• Diploma or Degree in Electrical / Mechanical Engineering or a related professional certification.
• Able to create/interpret (2D & 3D Cable/Mechanical Drawings, Bill of Material, Operating Procedures, Test Procedures, schematic and Interconnection Diagram, etc)
• General knowledge of Mechanical and Electrical Engineering.
• Good communication and leadership skills; able to train and guide junior technicians.
• Proficient in CAD software.
• Proficient in Microsoft Office with hand-on experience with data and Microsoft Excel reporting.

Kindly apply through ANY of the following methods:

• Submit your application by clicking the APPLY button;
• Email your resume to Job@anradus.com.sg. Please indicate #81261 on the email subject.

Anradus Application Policy: We value each application and ensure every resume is reviewed. Our process is efficient, typically concluding within 3 working days. If you do not receive communication from us within this timeframe, it's likely that your application has not been shortlisted by our client. In such cases, we recommend continuing your job search to maximize your opportunities.

Anradus Pte Ltd | EA License No. 20C0161 | Angel Lim | EA Reg No.: R1769781

Job Description & Requirements

• Involved in design and development of embedded and fiber optics sensing systems, and data communication IC’s hardware and software implementation to prototype functional testing.
• Data compilation and analysis, reporting and documentation.
• Involved in testing of photonics devices and/or optical sensors.
• Participates in the development and implementation of new products or product changes by creating product specifications, quality specifications, quality plans, risk analyses, FMEAs in conjunction with other product development team members.
• Runs complex problem solving efforts and mentors others on best practices. e.g. FMEA, Control Plan, Test plan, quality tools and DOE. e.g. Leads/ coordinates CA of failures using a structured approach.
• Owner of product specification and performance to those specifications.

Requirements

Qualifications:

• Candidate must possess at least a Bachelor or Master in Engineering (Electrical/Electronics/Computer/Optics)

Experience:

• 8 – 10 years working experience preferably in the semiconductor/component manufacturing industry background (with or without experience are welcome to apply)
• Software knowledge of MS Office, JMP, PDF/Spot-fire is a plus
• Excellent inter-personal and communication skills, both written and oral.
• Possess the ability to work independently, self-motivated, initiative and deliver tasks on time.
• Must be team oriented, positive working attitude, able to multi-tasks in a fast pace environment and work with personnel at all level.