Total 13 network engineer job vacancies in Art / Design / Entertainment category in Singapore

• Support execution of physical design flow for SoC projects under guidance from senior engineers
• Assist in Place and Route (PnR) activities to help optimize chip layout, performance, and power
• Participate in basic sign-off checks including Design Rule Check (DRC), Layout Versus Schematic (LVS), and Static Timing Analysis (STA)
• Learn and use EDA tools such as Genus, Innovus, Quantus, and RedHawk for design implementation and analysis
• Support development of simple TCL and Perl scripts to automate routine design tasks
• Work closely with design and verification teams to understand issues and support resolution of design challenges

Required competencies and certifications

• Master’s /degree in Electrical Engineering or related field
• Proficiency in TCL and Perl scripting for design automation
• Expertise in handling EDA tools for SoC top-level physical design, including Genus, Innovus, Quantus, and Redhawk
• Experience physical design flow

Candidates who do not meet the above experience requirements but possess a background in back-end semiconductor design are encouraged to apply.

EA: 25C2690/ R23115755

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team

Requirements

• Minimum MSEE, or BSEE, or related/equivalent discipline
• Experience / knowledge in RTL, C/C++ programming and verification
• Strong debugging and problem-solving skills
• Good communication and interpersonal skills
• Results-oriented and adaptable to changes
• C++/SystemC knowledge with High Level Synthesis experience is a plus.
• Experience / knowledge in CMOS Image Sensor is a plus

Responsibilities:

• Coordinate with Construction Teams, QPS, and Client for design works.
• Prepare Geotechnical engineering designs/ analysis such as deep excavation, slope stability, tunneling, shallow and deep foundation, pipe jacking, ground improvement etc.
• Prepare Civil and Structural engineering designs such as box culvert, ECM, construction and traffic deck steel strutting
• Propose monitoring plan and monitor the performance of project
• Strong in structural and geotechnical principals and good knowledge of Design Codes.
• Conversant in numerical modelling and knowledgeable in Plaxis/Slope-W and/or ETABS, SAFE, STAAD Pro, TEDDS an advantage
• Familiar with all local authorities’ regulations and submissions

Requirements:

• Civil / Structural discipline with qualification accredited by JAC of IES/ACES as QSS
• Minimum 8 years of local relevant design experience in Construction industry
• Well-versed with local standards and safety requirements in the construction industry.
• Good analytical, communication and interpersonal skills

Key Responsibilities Key Responsibilities

RTL Design and Verification

• Develop synthesizable RTL in Verilog/SystemVerilog for custom on-chip test, monitoring, and diagnostic IP targeting analog and mixed-signal failure detection.
• Design and verify digital logic blocks such as test controllers, sequencing logic, sensor/interface control logic, measurement and monitoring logic, data capture and comparison logic, and failure detection and reporting logic.
• Build clean register and bus-connected interfaces, for example APB, AHB, or AXI-lite based control and status paths, to enable firmware interaction and subsystem integration.
• Develop testbenches, assertions, checkers, and block or subsystem-level verification environments to validate controller behavior, detection logic, configuration programming, fault response, and status reporting.
• Plan and execute functional verification for normal, corner, negative, and fault-injection scenarios, with adequate coverage of critical diagnostic behaviors.
• Collaborate with analog and mixed-signal designers to create or use behavioral models, stubs, and interface abstractions for realistic verification of failure mechanisms and observability paths.
• Debug RTL and simulation issues through waveform analysis, assertion-based checks, root-cause investigation, and close interaction with integration and product teams.
• Ensure the RTL is modular, reusable, timing-aware, synthesis-friendly, and scalable for integration across multiple SoC derivatives.

SoC Integration

• Integrate custom DFT / diagnostic IP into SoC subsystems and system-level test architecture with proper consideration for clock/reset structure, interrupt handling, and status visibility.
• Work closely with SoC integration and DFT teams to ensure compatibility with system test infrastructure, production test flows, diagnostic mechanisms, and firmware control requirements.
• Support integration readiness by addressing CDC, reset interactions, timing considerations, low-power implications, and implementation handoff requirements.

Cross-Functional Collaboration

• Work closely with digital, analog, and mixed-signal design teams, DFT engineers, SoC architects, and product/test engineering teams throughout the design and validation cycle.
• Translate analog or mixed-signal failure modes into robust digital detection logic suitable for on-chip test, screening, and diagnosis.
• Contribute to technical discussions on architecture tradeoffs, observability strategy, and practical silicon debug readiness.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, with 5–7 years of relevant experience.
• Strong hands-on experience in RTL design using Verilog/SystemVerilog.
• Practical experience in RTL verification, simulation, and debugging methodologies.
• Solid understanding of ASIC / SoC design flow including coding, simulation, synthesis, and integration.
• Good foundation in digital design concepts such as FSM design, datapath design, bus protocols (AXI/AHB/APB), clock-domain handling, reset strategy, and timing considerations.
• Experience working in complex SoC environments with cross-functional teams.

Preferred Qualifications

• Experience developing control, monitoring, or diagnostic IP associated with analog or mixed-signal subsystems.
• Exposure to behavioral modeling or interface definition for analog and mixed-signal verification use cases.
• Familiarity with subsystem-level integration, production screening considerations, and silicon debug support.
• Working knowledge of scripting or automation for verification, regression, or design productivity is an advantage.

Description:

• You would be part of a dynamic digital SoC design team that develops state-of-the-art video processing, neural processing, advanced video analytics accelerators, and the entire Camera Processor SoC. You would be joining the team to explore, evaluate and define innovative design SoC architectures, to meet or exceed the technical requirements of the SoC. You would be responsible for the successful implementation of the designs in Verilog/SystemVerilog coding, metrics measurement to meet key objectives & results, and follow-through in comprehensive verifications to successful silicon.

Requirements:

• Experience in SoC architecture and design, and RTL coding with Verilog/SystemVerilog
• Experience in ARM or RISC-V processor system
• Experience in embedded C and assembly code programming
• Experience in analysis of power, timing and area
• Experience in at least one of scripting languages (e.g. Perl, Python, TCL, or Bash)
• Disciplined, quality-minded, and highly driven for excellence
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience
• Experience in always-on system, automotive system, secured system, bus interconnect, neural processing, video processing and video analytics is a plus
• Experience in system modelling and simulation using emulator and SystemC is a plus
• Experience in UVM verification methodology is a plus
• Passionate and strong in general programming is a plus

Responsibilities

1. Develop design requirements for an NPU based on system-level specifications.
2. Being part of modelling the performance of the NPU module and its data transaction throughput.
3. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU.
4. Understanding the mathematics of different convolution operators including different arithmetic formats (fixed point and floating point)
5. Estimate, measure and optimize PPA (Performance / Power / Area) to meet key objectives and results.
6. Optimizing micro-architecture design for low power and area is required.
7. Work closely with verification engineers to ensure comprehensive testing and debug any issues.
8. Support integration into the overall system, conducting design checks, and addressing lint/timing/CDC issues.
9. Collaborate with software teams to assist in compiler and toolchain development and their debugging.
10. Produce clear and concise design documentation.

Requirements

1. 5+ years of digital design with at least 2 to 3 years of SoC design experience is preferred.
2. At least one cycle of NPU design completion experience is required.
3. Hands on experience in digital design is a must.
4. Experience in microarchitecture design, and RTL coding with Verilog/ System-Verilog.
5. Experience in synthesis, with analysis of power, timing and area.
6. Disciplined, quality-minded, and highly driven for excellence.
7. Excellent team player and good communication skills.
8. MSEE/BSEE in Electrical Engineering or Computer Engineering.
9. Understanding of convolution operator and number system is required.
10. Candidates with relevant experiences would be offered as Senior, taking on higher responsibilities.
11. Experience in UVM verification methodology is a plus.
12. A plus to have SoC design experience.
13. Experience with optimizing micro-architectures for low-power and low-area is a plus.
14. Knowledge in deep learning algorithms such as CNN / Transformer is a plus.
15. Experience with past design experience with NPU / GPU / DSP design is a plus.
16. Experience with ARM or RISC-V processor systems is a plus.
17. Passionate and strong in general programming is a plus.

Description:

• You would be part of a dynamic digital SoC design team that develops state-of-the-art video processing, neural processing, advanced video analytics accelerators, and the entire Camera Processor SoC. You would be joining the team to explore, evaluate and define innovative design SoC architectures, to meet or exceed the technical requirements of the SoC. You would be responsible for the successful implementation of the designs in Verilog/SystemVerilog coding, metrics measurement to meet key objectives & results, and follow-through in comprehensive verifications to successful silicon.

Requirements:

• Experience in SoC architecture and design, and RTL coding with Verilog/SystemVerilog
• Experience in ARM or RISC-V processor system
• Experience in embedded C and assembly code programming
• Experience in analysis of power, timing and area
• Experience in at least one of scripting languages (e.g. Perl, Python, TCL, or Bash)
• Disciplined, quality-minded, and highly driven for excellence
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience
• Experience in always-on system, automotive system, secured system, bus interconnect, neural processing, video processing and video analytics is a plus
• Experience in system modelling and simulation using emulator and SystemC is a plus
• Experience in UVM verification methodology is a plus
• Passionate and strong in general programming is a plus

Position Overview:

• As a design verification engineer, you will be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space.

Requirements:

• Experience in UVM verification methodology
• Disciplined, quality-minded, and highly driven for excellence,
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience, but are open to fresh graduates with outstanding results
• Candidates with relevant experiences would be offered as Staff or Sr. Staff, taking on higher responsibilities
• Experience in video processing and video analytics is a plus
• Passionate and strong in general programming is a plus

Responsibilities:

1. Develop design requirements for an NPU based on system-level specifications.
2. Being part of modelling the performance of the NPU module and its data transaction throughput.
3. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU.
4. Understanding the mathematics of different convolution operators including different arithmetic formats (fixed point and floating point)
5. Estimate, measure and optimize PPA (Performance / Power / Area) to meet key objectives and results.
6. Optimizing micro-architecture design for low power and area is required.
7. Work closely with verification engineers to ensure comprehensive testing and debug any issues.
8. Support integration into the overall system, conducting design checks, and addressing lint/timing/CDC issues.
9. Collaborate with software teams to assist in compiler and toolchain development and their debugging.
10. Produce clear and concise design documentation.

Requirements

1. 8+ years of digital design with at least 2 to 3 years of SoC design experience is preferred.
2. At least one cycle of NPU design completion experience is required.
3. Hands on experience in digital design is a must.
4. Preferably has lead a team of at least 3 to 4 people in the past at the capacity of a design lead.
5. Experience in microarchitecture design, and RTL coding with Verilog/ System-Verilog.
6. Experience in synthesis, with analysis of power, timing and area.
7. Disciplined, quality-minded, and highly driven for excellence.
8. Excellent team player and good communication skills.
9. MSEE/BSEE in Electrical Engineering or Computer Engineering.
10. Understanding of convolution operator and number system is required.
11. Candidates with relevant experiences would be offered as Senior, taking on higher responsibilities.
12. Experience in UVM verification methodology is a plus.
13. A plus to have SoC design experience.
14. Experience with optimizing micro-architectures for low-power and low-area is a plus.
15. Knowledge in deep learning algorithms such as CNN / Transformer is a plus.
16. Experience with past design experience with NPU / GPU / DSP design is a plus.
17. Experience with ARM or RISC-V processor systems is a plus.
18. Passionate and strong in general programming is a plus.

Position Overview:

• As a design verification engineer, you will be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space.

Requirements:

• Experience in UVM verification methodology
• Disciplined, quality-minded, and highly driven for excellence,
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience, but are open to fresh graduates with outstanding results
• Candidates with relevant experiences would be offered as Senior or Staff, taking on higher responsibilities
• Experience in video processing and video analytics is a plus
• Passionate and strong in general programming is a plus

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team

Requirements

• Minimum MSEE, or BSEE, or equivalent, plus 3+ years of Digital Design and verification related experience
• Experience / knowledge in CMOS Image Sensor and Image Signal Processing (ISP)
• Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.
• Strong debugging and problem-solving skills
• Good communication and interpersonal skills
• Results oriented and adaptable to changes

Senior Design Engineer

• Working Location: Jurong East

• Working Days: Monday - Friday

• Working Hours: 8:30am - 5:15pm

• Salary range: SGD 5,500 to SGD 8,000 monthly, 13th month, SGD 250 transport allowance

Basic Functions

Specialize in customization on electrical design work related to diesel generator sets, synchronizing system, switchgears, controllers and associated equipment. Design drawings, BOM for factory production fabricating. Preparing documentation for approval. Integration with other equipment industry, such as generators protection, switchgears, BMS, etc.

Specific Responsibilities

1. Design & produce electrical drawings, BOM and documentation for factory production

2. Understands the ISO standards and various regions standards for design considerations

3. Works closely with procurement to engage and qualify suppliers and parts

4. Works closely with manufacturing team in the electrical installations of the product and ensures smooth flow in the production line

5. Have good understanding of generator controller and alternator working concepts

6. Works closely with Industrial Solutions and sales to understand the design requirements and provide timely response to tender submission

7. Support in testing and validation of design including parameter optimization for controllers, governors, AVR, PLCs, HMI 

8. Design & Program various controllers, PLCs, HMI if necessary

9. Provides on-site and remote troubleshooting support if needed

10. Lead in continuous improvement projects to reduce costs and improve work efficiency

11. Assists in managing, training, developing and mentoring junior engineers, ensure standard engineering practice among the engineers

Qualifications / Requirements

• Degree in Electrical Engineering with 7-8 years of relevant experience; or

• Diploma in Electrical Engineering with 10-12 years of relevant experience

• Required to be skilled in SEE Electrical.

• Experience in process change management tools and methodologies

• Specialized skills or subject matter expert in electrical related field will be an advantage 

• Knowledge in PLC electrical design, controllers, generators, switchgears and transformers

LIEW ONN KEE REG NO : R22108518

THE SUPREME HR ADVISORY EA NO:14C7279 

My Client:

My client is a global technology company focused on advanced semiconductor and high-performance computing systems. The engineering team is dedicated to building next-generation ASIC solutions across advanced process nodes, supporting large-scale compute-intensive applications.The team operates in a highly technical and fast-paced environment, with strong emphasis on physical implementation, performance optimization, and full-chip delivery. They are currently expanding their physical design team to support growing project demands across advanced nodes.

Job Responsibilities:

• Perform end-to-end physical design implementation from netlist to GDSII for advanced ASIC projects.
• Work on key stages including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and optimization.
• Drive timing closure across MMMC scenarios, including setup/hold fixing, clock optimization, and ECO implementation.
• Conduct physical verification and signoff tasks (DRC, LVS, IR drop, EM analysis) to ensure tape-out readiness.
• Optimize power, performance, and area (PPA) through iterative design improvements.
• Collaborate closely with front-end design, DFT, and signoff teams to resolve integration and late-stage issues.
• Contribute to design methodology improvements and automation through scripting and tooling enhancements.

Job Requirements:

• Bachelor’s degree or above in Microelectronics, Electronic Engineering, or related fields.
• Understanding of physical design flow and IC development process.
• Familiarity with PnR tools such as ICC2, Fusion Compiler, or Innovus.
• Knowledge of timing analysis, power optimization, and physical verification concepts.
• Basic scripting skills (TCL / Python / Shell) for automation is a plus.
• Strong learning ability and willingness to work in advanced technology environments.

What They Offer:

• Opportunity to work on cutting-edge semiconductor projects at advanced technology nodes.
• Exposure to full-chip design flow and large-scale ASIC development.
• Competitive compensation and long-term growth opportunities.

About Us

Dada Consultants was established in 2017, with the commitment of providing the best recruitment services in Singapore. We are comprised of a dynamic head-hunting team dedicated to sourcing for highly competent professionals in IT industry. We provide enterprises with customized talent solutions, and bring talents to career advancement.

If it sounds like your next move, please don’t hesitate to apply. Kindly note that only shortlisted candidates will be contacted. Appreciate your understanding. Data provided is for recruitment purposes only.

www.dadaconsultants.com

EA Registration Number: R2197058

Business Registration Number: 201735941W. Licence Number: 18S9037