Job Posting: Digital IC Design Engineer (Campus/New Grad/Experienced)
Position Type: Full-time
Location: Singapore
Posting Date: April 1, 2026
About Us
We are a cutting-edge chip design company based in Singapore with a global vision, specializing in artificial intelligence, high-performance computing, and next-generation core chip solutions. We are committed to innovation at the technological forefront. In the vibrant tech hub of Singapore, we provide an exceptional platform to transform academic theory into world-class products.
Responsibilities
- Core RTL Development: Perform block-level or subsystem-level digital circuit design, implementation, and optimization using Verilog HDL. Write high-quality, synthesizable RTL code.
- Chip Front-End Flow: Participate in the complete IC design front-end flow, including architecture exploration, logic synthesis, formal verification, static timing analysis (STA), and low-power design.
- Design Verification Collaboration: Work closely with the verification team, understand verification plans, assist in debugging, and ensure design functionality and performance meet targets.
- Technical Documentation: Prepare clear design specifications, implementation plans, and review documents.
Qualifications
[For Experienced Engineers (1+ years of experience)]
- Required Skills:Master's or Bachelor's degree in Microelectronics, Electronic Engineering, Computer Engineering, or a related field.Proficient in Verilog/VHDL with a solid foundation in digital IC design and RTL coding. Proven experience in successful block-level delivery through to tape-out.Familiar with the complete ASIC/SoC front-end design flow and related tools (e.g., Synopsys/Cadence suite).
- Preferred Qualifications:Experience in any of the following domains: CPU/GPU microarchitecture, high-speed interfaces (PCIe, DDR), AI accelerators, networking.Familiar with on-chip bus protocols (e.g., AMBA) and scripting languages (Python/Tcl).
[For New Graduates / Interns]
- Educational Background: We enthusiastically welcome applications from outstanding students (final-year undergraduate or Master's) or recent graduates from top global universities. We strongly encourage candidates with backgrounds in Microelectronics, Electronic Engineering, or Computer Science from Nanyang Technological University (NTU), National University of Singapore (NUS), or equivalent institutions to apply.
- Core Aptitude:Possess a high passion for chip design and a solid theoretical foundation in digital circuits.Proficient in the Verilog hardware description language, with hands-on RTL design practice from course projects or research.Understanding of fundamental digital design processes (e.g., logic synthesis, simulation, verification).
- Projects & Abilities:Outstanding performance in FPGA projects, digital design competitions, or related research projects is a plus.Excellent learning, analytical, and problem-solving skills.Strong communication skills in both English and Chinese, and a collaborative team spirit.
Why Join Us
- Work on Core Technology, Define the Future: Get directly involved in cutting-edge chip design projects. Your code will be transformed into silicon that changes the world.
- Exceptional Mentorship & Team: Collaborate with seasoned experts from leading companies in the industry, gaining invaluable career guidance and accelerating your growth.
- Competitive Compensation & Benefits:We offer a highly competitive salary in the Singapore market.A generous annual learning and development allowance to support conference attendance, training, and further education.
- Connected to Top Academic Networks: We highly value our connections with local top-tier institutions (like NTU, NUS) and provide an ideal bridge from campus to career for outstanding students.
How to Apply
If you are an experienced design expert or a rising star from institutions like NTU, NUS eager to build a career in the chip design field, we cordially invite you to join us!
Please send your English and Chinese resumes to: [zhuguangxing@smart-core.cn]. We are committed to reviewing every application carefully and will promptly arrange interviews with promising candidates.
招聘职位：数字IC设计工程师 (校招/应届/经验岗)
职位类型： 全职
工作地点： 新加坡
发布日期： 2026年4月1日
关于我们
我们是一家立足新加坡、面向全球的尖端芯片设计公司，专注于为人工智能、高性能计算及下一代核心芯片解决方案。我们致力于在技术的源头进行创新。在新加坡这个充满活力的科技中心，我们为您提供一个能将学术理论转化为世界级产品的绝佳平台。
岗位职责
- 核心RTL开发：使用Verilog HDL进行模块级或子系统级的数字电路设计、实现与优化，编写高质量、可综合的RTL代码。
- 芯片前端流程：参与完整的IC设计前端流程，包括架构探索、逻辑综合、形式验证、静态时序分析（STA）及低功耗设计。
- 设计验证协同：与验证团队紧密合作，理解验证计划，协助调试，确保设计功能与性能达标。
- 技术文档：撰写清晰的设计规格、实现方案及评审文档。
任职要求
【对经验工程师的要求 (1年以上经验)】
- 必备技能：
- 微电子/电子工程/计算机工程相关专业硕士或学士学位。
- 精通Verilog/VHDL，具备扎实的数字IC设计与RTL编码功底，有模块级交付至流片的成功经验。
- 熟悉ASIC/SoC前端设计全流程及工具（如Synopsys/Cadence系列）。
- 优先条件：
- 在以下任一领域有经验：CPU/GPU微架构、高速接口（PCIe, DDR）、AI加速器、网络处理。
- 熟悉AMBA等片上总线协议及脚本语言（Python/Tcl）。
【对应届生/在校实习生的要求】
- 教育背景：我们热烈欢迎来自全球顶尖大学的优秀在读学生（本科或硕士生）或应届毕业生申请。特别鼓励拥有南洋理工大学、新加坡国立大学或同等水平院校微电子、电子工程、计算机科学背景的同学投递简历。
- 核心潜力：
- 对芯片设计抱有极高热情，具备扎实的数字电路理论基础。
- 熟练掌握Verilog硬件描述语言，并有课程项目或课题研究中的RTL设计实践经验。
- 了解数字设计基本流程（如逻辑综合、仿真验证）。
- 项目与能力：
- 在FPGA项目、数字设计竞赛或相关科研项目中表现突出者优先。
- 出色的学习能力、分析能力和解决问题的能力。
- 良好的中英文沟通能力及团队协作精神。
为什么加入我们
- 深耕核心，定义未来：直接参与最前沿的芯片设计项目，您的代码将直接转化为改变世界的硅晶片。
- 卓越的导师与团队：与来自行业领先公司的资深专家共事，获得宝贵的职业指导与快速成长。
- 有竞争力的薪酬与福利：
- 提供新加坡市场极具竞争力的薪资。
- 丰厚的年度学习与发展津贴，支持您参加会议、培训和深造。
- 连接顶尖学术网络：我们高度重视与本地顶尖学府（如NTU, NUS）的联系，为优秀学子提供从校园到职场的完美衔接。
申请方式
如果您是经验丰富的设计专家，或是来自NTU、NUS等高校、渴望在芯片设计领域开创事业的明日之星，我们诚邀您的加入！
请将您的中英文简历发送至：[zhuguangxing@smart-core.cn]，我们承诺将对每一份申请予以认真评估，并尽快安排与潜力候选人的面试
