Total 382 system engineer job vacancies in Art / Design / Entertainment category

Key Responsibilities Key Responsibilities

RTL Design and Verification

• Develop synthesizable RTL in Verilog/SystemVerilog for custom on-chip test, monitoring, and diagnostic IP targeting analog and mixed-signal failure detection.
• Design and verify digital logic blocks such as test controllers, sequencing logic, sensor/interface control logic, measurement and monitoring logic, data capture and comparison logic, and failure detection and reporting logic.
• Build clean register and bus-connected interfaces, for example APB, AHB, or AXI-lite based control and status paths, to enable firmware interaction and subsystem integration.
• Develop testbenches, assertions, checkers, and block or subsystem-level verification environments to validate controller behavior, detection logic, configuration programming, fault response, and status reporting.
• Plan and execute functional verification for normal, corner, negative, and fault-injection scenarios, with adequate coverage of critical diagnostic behaviors.
• Collaborate with analog and mixed-signal designers to create or use behavioral models, stubs, and interface abstractions for realistic verification of failure mechanisms and observability paths.
• Debug RTL and simulation issues through waveform analysis, assertion-based checks, root-cause investigation, and close interaction with integration and product teams.
• Ensure the RTL is modular, reusable, timing-aware, synthesis-friendly, and scalable for integration across multiple SoC derivatives.

SoC Integration

• Integrate custom DFT / diagnostic IP into SoC subsystems and system-level test architecture with proper consideration for clock/reset structure, interrupt handling, and status visibility.
• Work closely with SoC integration and DFT teams to ensure compatibility with system test infrastructure, production test flows, diagnostic mechanisms, and firmware control requirements.
• Support integration readiness by addressing CDC, reset interactions, timing considerations, low-power implications, and implementation handoff requirements.

Cross-Functional Collaboration

• Work closely with digital, analog, and mixed-signal design teams, DFT engineers, SoC architects, and product/test engineering teams throughout the design and validation cycle.
• Translate analog or mixed-signal failure modes into robust digital detection logic suitable for on-chip test, screening, and diagnosis.
• Contribute to technical discussions on architecture tradeoffs, observability strategy, and practical silicon debug readiness.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, with 5–7 years of relevant experience.
• Strong hands-on experience in RTL design using Verilog/SystemVerilog.
• Practical experience in RTL verification, simulation, and debugging methodologies.
• Solid understanding of ASIC / SoC design flow including coding, simulation, synthesis, and integration.
• Good foundation in digital design concepts such as FSM design, datapath design, bus protocols (AXI/AHB/APB), clock-domain handling, reset strategy, and timing considerations.
• Experience working in complex SoC environments with cross-functional teams.

Preferred Qualifications

• Experience developing control, monitoring, or diagnostic IP associated with analog or mixed-signal subsystems.
• Exposure to behavioral modeling or interface definition for analog and mixed-signal verification use cases.
• Familiarity with subsystem-level integration, production screening considerations, and silicon debug support.
• Working knowledge of scripting or automation for verification, regression, or design productivity is an advantage.

Description:

• You would be part of a dynamic digital SoC design team that develops state-of-the-art video processing, neural processing, advanced video analytics accelerators, and the entire Camera Processor SoC. You would be joining the team to explore, evaluate and define innovative design SoC architectures, to meet or exceed the technical requirements of the SoC. You would be responsible for the successful implementation of the designs in Verilog/SystemVerilog coding, metrics measurement to meet key objectives & results, and follow-through in comprehensive verifications to successful silicon.

Requirements:

• Experience in SoC architecture and design, and RTL coding with Verilog/SystemVerilog
• Experience in ARM or RISC-V processor system
• Experience in embedded C and assembly code programming
• Experience in analysis of power, timing and area
• Experience in at least one of scripting languages (e.g. Perl, Python, TCL, or Bash)
• Disciplined, quality-minded, and highly driven for excellence
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience
• Experience in always-on system, automotive system, secured system, bus interconnect, neural processing, video processing and video analytics is a plus
• Experience in system modelling and simulation using emulator and SystemC is a plus
• Experience in UVM verification methodology is a plus
• Passionate and strong in general programming is a plus

Responsibilities

1. Develop design requirements for an NPU based on system-level specifications.
2. Being part of modelling the performance of the NPU module and its data transaction throughput.
3. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU.
4. Understanding the mathematics of different convolution operators including different arithmetic formats (fixed point and floating point)
5. Estimate, measure and optimize PPA (Performance / Power / Area) to meet key objectives and results.
6. Optimizing micro-architecture design for low power and area is required.
7. Work closely with verification engineers to ensure comprehensive testing and debug any issues.
8. Support integration into the overall system, conducting design checks, and addressing lint/timing/CDC issues.
9. Collaborate with software teams to assist in compiler and toolchain development and their debugging.
10. Produce clear and concise design documentation.

Requirements

1. 5+ years of digital design with at least 2 to 3 years of SoC design experience is preferred.
2. At least one cycle of NPU design completion experience is required.
3. Hands on experience in digital design is a must.
4. Experience in microarchitecture design, and RTL coding with Verilog/ System-Verilog.
5. Experience in synthesis, with analysis of power, timing and area.
6. Disciplined, quality-minded, and highly driven for excellence.
7. Excellent team player and good communication skills.
8. MSEE/BSEE in Electrical Engineering or Computer Engineering.
9. Understanding of convolution operator and number system is required.
10. Candidates with relevant experiences would be offered as Senior, taking on higher responsibilities.
11. Experience in UVM verification methodology is a plus.
12. A plus to have SoC design experience.
13. Experience with optimizing micro-architectures for low-power and low-area is a plus.
14. Knowledge in deep learning algorithms such as CNN / Transformer is a plus.
15. Experience with past design experience with NPU / GPU / DSP design is a plus.
16. Experience with ARM or RISC-V processor systems is a plus.
17. Passionate and strong in general programming is a plus.

1.       Determined appropriate construction methods, materials, and quality standards by reviewing and coordinating structural design and shop drawings to ensure compliance with project specifications and relevant codes.

2.       Drafted, interpreted, and reviewed engineering drawings, technical specifications, and construction procedures to ensure accuracy, constructability, and adherence to design intent.

3.       Coordinated with consultants, contractors, and fabrication teams to resolve technical design issues and implement necessary drawing amendments.

4.       Prepared and submitted technical documentation, including design approval requests and revised drawings, ensuring proper document control and compliance with quality management systems.

5.       Monitored design modifications, assessed their impact on construction methodology and project progress, and facilitated necessary revisions to maintain alignment with approved designs.

6.       Reviewed and checked structural design calculations provided by consultants for temporary and permanent works, ensuring operation team can met design requirements and were suitable for safe execution.

7.       Established and maintained coordination between design and site teams to support effective execution of construction activities.

8.       Provided technical support to the construction team by addressing reinforcement and structural queries raised during inspections and site activities.

9.       Maintained updated records of structural components and construction progress to ensure accurate documentation and tracking of completed works.

about the job. An exciting opportunity has arisen for a technical specialist to spearhead the development and maintenance of cutting-edge data architecture and next-generation intelligence tools.

• Drive the design, deployment, and optimization of corporate analytics repositories and cloud-native architecture.

• Build and integrate highly scalable pipelines for data transformation, ingestion, and storage using cloud services.

• Oversee data quality, security protocols, governance frameworks, and overall infrastructural reliability.

• Conceptualize and implement advanced language model applications, cognitive assistants, and automated workflow solutions.

• Monitor industrial trends to implement modern digital capabilities and optimize current organizational operations.

skills and experience required.

- Strong hands-on experience in ETL/ELT pipeline development
- Proficient in data transformation, cleaning, and modeling
- Good experience with SQL and working with large datasets
- Familiar with Airflow, AWS Glue ,S3 , Redshift , Lambda
- Experience working with LLMs (e.g. OpenAI, Claude, or QWEN)

To apply online please use the apply function, alternatively you may contact Chloe Chen at chloe.chen(@)randstad.com.sg. (EA: 94C3609 /R1768253)

JOB-00548

What You’ll Do (Key Responsibilities)

• Advanced Layout Design: Architect multi-layer, high-density PCBs for complex satellite communication equipment, managing critical constraints like signal integrity (SI), power integrity (PI), and thermal management.

• RF & High-Speed Routing: Execute impedance-controlled routing, grounding strategies, and microwave-frequency layouts for critical RF components (SSPAs, BUCs, LNAs).

• End-to-End Execution: Drive the entire ECAD workflow using Altium Designer (or equivalent)—from schematic capture and library management to generating production-ready manufacturing packages (Gerber, ODB++, pick-and-place).

• Simulation & Validation: Utilize RF simulation tools (HFSS, AWR) to optimize board performance and minimize EMI/EMC risks before fabrication.

• Lab Testing & Bring-Up: Roll up your sleeves in the lab to support prototype assembly, board bring-up, debugging, and root-cause analysis using spectrum analyzers, network analyzers, and oscilloscopes.

• Design for Excellence (DFX): Partner with manufacturing teams to conduct DFM/DFA reviews, ensuring seamless production scaling and strict adherence to IPC standards.

What You Bring (Qualifications & Experience)

• Education: Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Telecommunications, or a related discipline.

• Experience: 3–5+ years of proven experience in multi-layer PCB design, with a strong emphasis on RF, wireless, or telecommunications hardware.

• ECAD Expertise: High proficiency in Altium Designer, Cadence Allegro/OrCAD, or Mentor Graphics.

• Technical Depth: Deep understanding of analog, digital, mixed-signal, and high-speed digital layout techniques (controlled impedance, differential pairs).

• RF Component Familiarity: Working knowledge of RF communication building blocks like Transceivers, Down-Converters, BUCs, and LNAs.

• Lab Skills: Hands-on experience troubleshooting physical hardware using RF lab equipment (VNA, Spectrum Analyzers).

• Standards: Familiarity with IPC guidelines, EMI/EMC compliance, and aerospace/defense reliability standards.

Please submit your updated resume in Word format by using the Apply Now Button.

We regret that only shortlisted candidates will be notified.

Email resume to che••••••••••@peopleprofilers.com

People Profilers Pte Ltd, 20 Cecil Street, #08-09 PLUS Building, Singapore 049705

Tel: 69•• •744

Posting Personnel: Ding Xin Er

EA Licence Number: 02C4944

Registration Number: R22106669

Description:

• You would be part of a dynamic digital SoC design team that develops state-of-the-art video processing, neural processing, advanced video analytics accelerators, and the entire Camera Processor SoC. You would be joining the team to explore, evaluate and define innovative design SoC architectures, to meet or exceed the technical requirements of the SoC. You would be responsible for the successful implementation of the designs in Verilog/SystemVerilog coding, metrics measurement to meet key objectives & results, and follow-through in comprehensive verifications to successful silicon.

Requirements:

• Experience in SoC architecture and design, and RTL coding with Verilog/SystemVerilog
• Experience in ARM or RISC-V processor system
• Experience in embedded C and assembly code programming
• Experience in analysis of power, timing and area
• Experience in at least one of scripting languages (e.g. Perl, Python, TCL, or Bash)
• Disciplined, quality-minded, and highly driven for excellence
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience
• Experience in always-on system, automotive system, secured system, bus interconnect, neural processing, video processing and video analytics is a plus
• Experience in system modelling and simulation using emulator and SystemC is a plus
• Experience in UVM verification methodology is a plus
• Passionate and strong in general programming is a plus

Position Overview:

• As a design verification engineer, you will be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space.

Requirements:

• Experience in UVM verification methodology
• Disciplined, quality-minded, and highly driven for excellence,
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience, but are open to fresh graduates with outstanding results
• Candidates with relevant experiences would be offered as Staff or Sr. Staff, taking on higher responsibilities
• Experience in video processing and video analytics is a plus
• Passionate and strong in general programming is a plus

Responsibilities:

1. Develop design requirements for an NPU based on system-level specifications.
2. Being part of modelling the performance of the NPU module and its data transaction throughput.
3. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU.
4. Understanding the mathematics of different convolution operators including different arithmetic formats (fixed point and floating point)
5. Estimate, measure and optimize PPA (Performance / Power / Area) to meet key objectives and results.
6. Optimizing micro-architecture design for low power and area is required.
7. Work closely with verification engineers to ensure comprehensive testing and debug any issues.
8. Support integration into the overall system, conducting design checks, and addressing lint/timing/CDC issues.
9. Collaborate with software teams to assist in compiler and toolchain development and their debugging.
10. Produce clear and concise design documentation.

Requirements

1. 8+ years of digital design with at least 2 to 3 years of SoC design experience is preferred.
2. At least one cycle of NPU design completion experience is required.
3. Hands on experience in digital design is a must.
4. Preferably has lead a team of at least 3 to 4 people in the past at the capacity of a design lead.
5. Experience in microarchitecture design, and RTL coding with Verilog/ System-Verilog.
6. Experience in synthesis, with analysis of power, timing and area.
7. Disciplined, quality-minded, and highly driven for excellence.
8. Excellent team player and good communication skills.
9. MSEE/BSEE in Electrical Engineering or Computer Engineering.
10. Understanding of convolution operator and number system is required.
11. Candidates with relevant experiences would be offered as Senior, taking on higher responsibilities.
12. Experience in UVM verification methodology is a plus.
13. A plus to have SoC design experience.
14. Experience with optimizing micro-architectures for low-power and low-area is a plus.
15. Knowledge in deep learning algorithms such as CNN / Transformer is a plus.
16. Experience with past design experience with NPU / GPU / DSP design is a plus.
17. Experience with ARM or RISC-V processor systems is a plus.
18. Passionate and strong in general programming is a plus.

Position Overview:

• As a design verification engineer, you will be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space.

Requirements:

• Experience in UVM verification methodology
• Disciplined, quality-minded, and highly driven for excellence,
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience, but are open to fresh graduates with outstanding results
• Candidates with relevant experiences would be offered as Senior or Staff, taking on higher responsibilities
• Experience in video processing and video analytics is a plus
• Passionate and strong in general programming is a plus

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team

Requirements

• Minimum MSEE, or BSEE, or equivalent, plus 3+ years of Digital Design and verification related experience
• Experience / knowledge in CMOS Image Sensor and Image Signal Processing (ISP)
• Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.
• Strong debugging and problem-solving skills
• Good communication and interpersonal skills
• Results oriented and adaptable to changes

Electrical Engineer (Quality Control)

• Office: Jalan Besar / Lavender MRT
• Project Site: TUAS areas (Transport provided for designation MRT station to site office)
• Junior: $4000 to $4500, Senior: $4500 to $6000
• Working days: Mon to Fri 8/8.30am to 5/5.30pm, Sat may need works depends on site (if works 8 hours can claim allowances)

Requirements

• Diploma or Degree in Electrical Engineering or equivalent.
• At least 3-5 years’ experience in electrical QC for large-scale construction, industrial, or infrastructure projects.
• Strong knowledge of LV/MV electrical systems, standards, and QA/QC practices.

Job scopes

1) Implement and manage quality control procedures for electrical works on site.

2) Conduct inspections, audits, and testing of electrical installations, equipment, and materials.

3) Review and verify electrical shop drawings, material submissions, and method statements for compliance.

4) Monitor workmanship to ensure alignment with project specifications and quality standards.

5) Prepare non-conformance reports (NCRs), track corrective actions, and ensure timely closure.

6) Liaise with consultants, clients, and subcontractors to resolve quality related issues.

7) Maintain quality documentation, inspection records, and test reports.

8) Support handover and commissioning by ensuring all electrical quality requirements are met.

Interested applicants kindly submit your resume through here or Whatsapp +65 9019 3218 (Joevy), and allow our Consultant to match you with our Clients. No Charges will be incurred by Candidates for any service rendered.

Tan Yu Jing Reg No: R26161199

The Supreme HR Advisory Pte Ltd EA No: 14C7279

Electrical Engineer (Quality Control)

• Office: Jalan Besar / Lavender MRT
• Project Site: TUAS areas (Transport provided for designation MRT station to site office)
• Junior: $4000 to $4500, Senior: $4500 to $6000
• Working days: Mon to Fri 8/8.30am to 5/5.30pm, Sat may need works depends on site (if works 8 hours can claim allowances)

Requirements

• Diploma or Degree in Electrical Engineering or equivalent.
• At least 3-5 years’ experience in electrical QC for large-scale construction, industrial, or infrastructure projects.
• Strong knowledge of LV/MV electrical systems, standards, and QA/QC practices.

Job scopes

1) Implement and manage quality control procedures for electrical works on site.

2) Conduct inspections, audits, and testing of electrical installations, equipment, and materials.

3) Review and verify electrical shop drawings, material submissions, and method statements for compliance.

4) Monitor workmanship to ensure alignment with project specifications and quality standards.

5) Prepare non-conformance reports (NCRs), track corrective actions, and ensure timely closure.

6) Liaise with consultants, clients, and subcontractors to resolve quality related issues.

7) Maintain quality documentation, inspection records, and test reports.

8) Support handover and commissioning by ensuring all electrical quality requirements are met.

Interested applicants kindly submit your resume through here or Whatsapp +65 9019 3218 (Joevy), and allow our Consultant to match you with our Clients. No Charges will be incurred by Candidates for any service rendered.

Tan Yu Jing Reg No: R26161199

The Supreme HR Advisory Pte Ltd EA No: 14C7279

Electrical Engineer (Quality Control)

• Office: Jalan Besar / Lavender MRT
• Project Site: TUAS areas (Transport provided for designation MRT station to site office)
• Junior: $4000 to $4500, Senior: $4500 to $6000
• Working days: Mon to Fri 8/8.30am to 5/5.30pm, Sat may need works depends on site (if works 8 hours can claim allowances)

Requirements

• Diploma or Degree in Electrical Engineering or equivalent.
• At least 3-5 years’ experience in electrical QC for large-scale construction, industrial, or infrastructure projects.
• Strong knowledge of LV/MV electrical systems, standards, and QA/QC practices.

Job scopes

1) Implement and manage quality control procedures for electrical works on site.

2) Conduct inspections, audits, and testing of electrical installations, equipment, and materials.

3) Review and verify electrical shop drawings, material submissions, and method statements for compliance.

4) Monitor workmanship to ensure alignment with project specifications and quality standards.

5) Prepare non-conformance reports (NCRs), track corrective actions, and ensure timely closure.

6) Liaise with consultants, clients, and subcontractors to resolve quality related issues.

7) Maintain quality documentation, inspection records, and test reports.

8) Support handover and commissioning by ensuring all electrical quality requirements are met.

Interested applicants kindly submit your resume through here or Whatsapp +65 9019 3218 (Joevy), and allow our Consultant to match you with our Clients. No Charges will be incurred by Candidates for any service rendered.

Tan Yu Jing Reg No: R26161199

The Supreme HR Advisory Pte Ltd EA No: 14C7279

Electrical Engineer (Quality Control)

• Office: Jalan Besar / Lavender MRT
• Project Site: TUAS areas (Transport provided for designation MRT station to site office)
• Junior: $4000 to $4500, Senior: $4500 to $6000
• Working days: Mon to Fri 8/8.30am to 5/5.30pm, Sat may need works depends on site (if works 8 hours can claim allowances)

Requirements

• Diploma or Degree in Electrical Engineering or equivalent.
• At least 3-5 years’ experience in electrical QC for large-scale construction, industrial, or infrastructure projects.
• Strong knowledge of LV/MV electrical systems, standards, and QA/QC practices.

Job scopes

1) Implement and manage quality control procedures for electrical works on site.

2) Conduct inspections, audits, and testing of electrical installations, equipment, and materials.

3) Review and verify electrical shop drawings, material submissions, and method statements for compliance.

4) Monitor workmanship to ensure alignment with project specifications and quality standards.

5) Prepare non-conformance reports (NCRs), track corrective actions, and ensure timely closure.

6) Liaise with consultants, clients, and subcontractors to resolve quality related issues.

7) Maintain quality documentation, inspection records, and test reports.

8) Support handover and commissioning by ensuring all electrical quality requirements are met.

Interested applicants kindly submit your resume through here or Whatsapp +65 9019 3218 (Joevy), and allow our Consultant to match you with our Clients. No Charges will be incurred by Candidates for any service rendered.

Tan Yu Jing Reg No: R26161199

The Supreme HR Advisory Pte Ltd EA No: 14C7279