Total 131 structural engineer job vacancies in Bengaluru

Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.

We are seeking a highly motivated and innovative Staff IC Design Engineer (RTL Design) with strong experience in SoC development flows. In this role, you will play a pivotal part in the design and development of advanced integrated circuits that power Renesas MCU products. You will lead complex RTL design efforts, own key IP/subsystem deliverables, mentor junior engineers, and help evolve design methodologies and best practices.

Key Responsibilities

• Lead RTL design and development of complex IPs and subsystems within MCU SoCs, ensuring compliance with performance, power, and area (PPA) targets
• Drive micro-architecture definition and high-level digital design for assigned blocks
• Support SoC integration, delivering high-quality subsystem views and documentation to Back-end and Design Verification teams
• Own design quality checks, including lint, CDC, and RDC, and actively support functional verification of assigned blocks
• Collaborate closely with system architects, verification engineers, physical design teams, and software teams to define specifications and ensure seamless end-to-end integration
• Provide technical guidance and mentorship to junior engineers, raising overall team capability and design quality
• Contribute to continuous improvement of RTL design methodologies, coding guidelines, and design processes

At LinkedIn, our approach to flexible work is centered on trust and optimized for culture, connection, clarity, and the evolving needs of our business. The work location of this role is hybrid, meaning it will be performed both from home and from a LinkedIn office on select days, as determined by the business needs of the team.

At LinkedIn, the Productivity Engineering Site Reliability Engineering (SRE) team plays a critical role in ensuring our enterprise business applications are reliable, scalable, secure, and highly automated.
We are seeking a Senior Engineer,  Site Reliability (Sr. SRE) to design, build, and operate highly reliable systems that power mission-critical financial and enterprise applications.

In this role, you will partner closely with Development and SRE teams from early design through production, driving improvements in reliability, performance, and scalability across complex application ecosystems. You will collaborate with cross-functional infrastructure teams to modernize and scale financial systems platforms.
You will lead and contribute to key initiatives across application, database, and middleware layers, including performance optimization, observability, and modernization from legacy to modern platforms.
This is an exciting opportunity for an engineer who thrives on solving complex production challenges, driving automation at scale, and building resilient systems.

Responsibilities

• Partner with development teams to influence system design for reliability, scalability, and performance from early stages.
• Define and implement SRE practices including SLOs, SLAs, SLIs, error budgets, and operational readiness.
• Own end‑to‑end production and development operations, including monitoring, alerting, incident response, and root cause analysis.
• Troubleshoot and resolve issues across application, database, middleware, and infrastructure layers.
• Automate operational workflows to reduce manual effort and improve system reliability.
• Contribute to observability strategy across monitoring, logging, tracing, and alerting platforms.
• Build and improve internal tools and platforms to increase engineering productivity and operational efficiency.
• Improve deployment, release, and change management processes through automation and standardization.
• Perform performance tuning, capacity planning, and system optimization across distributed systems.
• Support modernization initiatives, including cloud migrations and adoption of new technologies.
• Collaborate across development, infrastructure, and business teams to deliver scalable solutions.
• Participate in on‑call rotations and support 24x7 production operations through shift‑based coverage.

The Senior Data Analytics Engineer will lead the design, development, and evolution of our enterprise analytics platform. This role blends hands on technical ownership with team leadership, offering the opportunity to shape both our data architecture and our analytics engineering practice.

You will own critical components of our Data Vault 2.0 warehouse on Snowflake, mentor a growing team of Analytics Engineers, and serve as the connective layer between raw operational data and business critical insights.

Our data environment goes well beyond a typical dbt project. We operate a mature, multi tenant analytics warehouse integrating 13+ source systems (including Five9, inContact, Serenova, Salesforce, Shiftboard, and NetSuite) across 15+ client engagements. You’ll work across the full analytics stack—from staging and raw vault to business vault, prime stage, and client specific information marts—delivering clean, tested, and well documented models that support finance, operations, and compliance reporting

As a System Engineer, you will be the technical backbone of our projects. You will translate our customers' vision into a concrete engineering reality. Your key responsibilities will include:

• Architecting the System: Act as the lead technical authority, translating customer needs into precise system-level requirements and specifications for our electric propulsion systems.
• Bridging the Gap: Deconstruct high-level vehicle requirements into detailed functional, performance, and non-functional requirements for our motor and MCU subsystems.
• Ensuring Excellence: Conduct in-depth system analysis focusing on performance, efficiency, and responsiveness. You will own the system testing and release strategy, adhering to the V-model development process.
• Defining Interactions: Master the complex interfaces between our system and the vehicle's inputs/outputs, defining everything from core functions to critical error-handling reactions.
• Guiding Software Development: Convert vehicle-level needs into actionable software function requirements, directly influencing how our systems behave.
• Driving Quality: Define, execute, and oversee comprehensive system verification and validation plans, ensuring our products are robust and reliable.

We need a strategic thinker with a good understanding of vehicle systems and a passion for problem-solving.

• You are a natural communicator, comfortable leading technical discussions with both customers and our internal engineering experts.
• You excel at troubleshooting complex issues, quickly identifying root causes and implementing effective solutions.
• You are a forward-thinker, eager to contribute to the development of our next-generation platform concepts for electric mobility.
• You are a mentor at heart, willing to guide and develop junior engineers and trainees.
• You are meticulous and organized, ensuring all technical documentation and reports are comprehensive and delivered on time.

Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.

Renesas India is seeking an experienced Staff / Senior Staff Physical Design Engineer to lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes. This role requires deep expertise in timing, congestion, power integrity, and clocking methodologies, along with strong cross-functional collaboration skills. While this role does not own SoC-level physical design, it plays a critical role in aligning subsystem implementation with overarching SoC strategies.

Key Responsibilities

• Lead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality
• Collaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements, without direct ownership of SoC-level execution
• Apply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture
• Develop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency
• Mentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption
• Work cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure
• Proactively identify, assess, and mitigate physical design risks, coordinating closely with SoC teams to manage impacts and drive solutions

Minimum 3 years of relevant overall experience in the project on-site supervision, should have good knowledge of codes / quality standards and various testing procedures to ensure quality assurance. c. Minimum 2 years of experience in project on-site supervision, should have good knowledge of codes / quality standards and various testing procedures to ensure quality assurance in water supply / used water management / sewerage systems. d. Having specific project experience in Karnataka. e. Knowing of Kannada language is preferable.

Roles & Responsibilities :
The candidate will be part of the “Communication Protocol and Hardware” team in MBRDI

• Develop test framework using CAPL for Ethernet Switch Testing

• GUI development using C# .NET framework

• Understanding of the Ethernet Switch/PHY configuration and functional behavior

• Understanding the software requirements and formulating the test specification

• Test report analysis and defect creation

• Should be able to develop transceiver drivers and applications on the embedded system, if needed

• Compiling, Flashing and Debugging of the embedded firmware

• Create HW test setup and test the requirements to capture test results with HW debugging, if needed
 

The Lead BI Engineer will be responsible for architecting, developing, and optimizing enterprise-scale business intelligence solutions. This role requires deep expertise in Power BI, Azure, Databricks, and SQL, with the ability to design scalable data pipelines, deliver advanced analytics, and drive BI adoption across the organization. The ideal candidate combines strong technical skills with leadership capabilities, guiding teams and collaborating with stakeholders to enable data-driven decision-making.

Key Responsibilities

Data Engineering & Pipeline Development

• Design and implement data ingestion pipelines from multiple sources using Azure Databricks.
• Develop scalable and reusable frameworks for ingesting and transforming datasets.
• Integrate end-to-end data pipelines ensuring data quality, consistency, and governance.
• Work with event-based/streaming technologies for real-time data ingestion and processing.
• Optimize Databricks code and perform performance tuning for large-scale workloads.

SQL Development & Optimization

• Strong expertise in SQL, T-SQL, and PL/SQL with hands-on experience in SQL Server.
• Write, analyze, and optimize complex SQL queries including stored procedures, functions, triggers, joins, updates, and constraints.
• Deep knowledge of SQL architecture: Agent Jobs, Indexes, Partitions, Views, and Procedures.
• Proven ability to design high-performance queries and implement best practices for SQL optimization.

BI & Visualization

• Lead the design and development of Power BI dashboards, reports, and KPI scorecards.
• Proficient in DAX, advanced calculations, and data modeling aligned with warehouse standards.
• Collaborate with business stakeholders to translate requirements into actionable BI solutions.
• Champion BI adoption and foster a culture of data-driven decision-making.

Cloud & Infrastructure

• Design and deploy data applications on Azure cloud solutions (Synapse, Data Lake, SQL DB, Blob Storage).
• Hands-on experience with Azure Data Factory, Azure Functions, and Azure DevOps for automation and orchestration.
• Provision and manage Databricks clusters, including scheduling and job automation.
• Familiarity with AWS/GCP integration where applicable.

Advanced Analytics & Development

• Experience with PySpark and Python for data processing and advanced analytics.
• Hands-on experience with Spark SQL, Spark Streaming, Delta Lake, and Scala/Python notebooks.
• Develop proofs of concept (POCs) and prototypes with customer teams.
• Implement transformational big data projects, including real-time streaming using Databricks.

We are looking for a Senior QA Engineer to help begin the India Localization team. As Pismo expands globally, we are looking to expand the number of features in different markets outside of the core platform. Working closely with Engineering and Product teams, they identify automation opportunities, uncover application faults, and promote best-in-class QA practices across the organization. The Senior QA Engineer supports end-to-end quality through robust test planning, exploratory and manual testing when required, and continuous adoption of emerging QA technologies. This role combines strong technical expertise in test frameworks, CI/CD-integrated automation, and performance testing with clear communication of quality metrics, test results, and risks.

What You'll Do 

• Work closely with Engineering and Product teams to identify new automation opportunities and application faults. 

• Collaborate with other QA professionals to promote best practices across the organization. 

• Develop and maintain QA tools and frameworks to support automated testing. 

• Stay up to date with emerging trends and technologies in the QA field. 

• Define and implement design principles for automated test procedures. 

• Write and maintain automation scripts integrated into software applications. 

• Support teams in developing complex end-to-end automated testing solutions and performance tests integrated with CI/CD pipelines. 

• Create and document detailed, comprehensive, and well-structured test plans and test cases. 

• Communicate test progress, results, and quality metrics effectively. 

• Identify quality issues, report bugs, and highlight problem areas. 

• Promote high-quality standards through reusable and scalable testing strategies. 

• Execute exploratory, usability, and manual tests when necessary. 

This is a hybrid position. Expectation of days in office will be confirmed by your hiring manager. 

Individual Contributor role for Technical leader with 2-5 years of experience in Analog and Power IC development within 2.6B$ Power Business Unit at Renesas. Primary responsibilities include leading the IP design blocks for development of power management ICs, including voltage regulators, power converters, and other related components and collaborate with cross-functional teams to ensure successful integration of ICs into larger systems. The candidate will work on a wide range of exciting and cutting edge PMICs, including Linear and Switching DC-DC converters powering the next generation of most sought-after phones and handheld devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio. This is an IC role with complete focus on product development and no people management.

Essential Functions:

· Identify and resolve technical challenges and risks.

· Should have a very good understanding of Power devices, operations and design trade-offs for better performance & reliability.

· Should be able to lead development and integration of complex I/Ps like +ve/-ve Charge Pumps, Source-Sink LDOs, Ultra-low power Oscillators (including Relaxation type), Temperature Sensor, Current Sense, SAR ADCs, House Keeping blocks, Protection (Thermal, Under-Voltage, Over-Voltage, Over Current etc) and other analog blocks including Bandgap references, V2I, Analog Buffers, Op-Amps, Comparators, High speed level shifters etc. Thorough understanding of Switch Cap circuits is a must.

· Must have in-depth understanding of and should be able to choose, design & compensate Control loops keeping in mind the target performance.

· Must be able to bring in innovative ideas to improve designs to meet challenging specifications and achieve better system performance.

· Should have in-depth knowledge of Analog layouts, FET layouts, Noise isolation techniques and be able to guide the layout development from floor planning till Chip Top completion and verification and do trade-offs based on desired performance.

· Must be conversant with the standard design, extraction and simulation flows & tools, speed, convergence, accuracy trade-offs and should be able to optimize setups based on Pre/Post (with/without) Parasitic using simulator options, debug and navigate through tool related challenges.

· Should be able to setup design flows and methodologies including checklists, reviews to ensure quality designs and take them all the way to Silicon success.

Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.

We are seeking a highly experienced IP Design Verification Engineer to join the Verification R&D team at Renesas. In this role, you will be a part of team responsible for SOC verification, ensuring first‑pass silicon success through building verification environment from scratch using best in class methodologies, metric‑driven verification, and intelligent coverage convergence using AI tools.

You will play a key technical role in defining verification strategies, architecting testbenches, defining Test Plans tracing Requirements, driving coverage closure using advanced automation and AI‑assisted techniques, and collaborating closely with Architecture, RTL, chip top, and Validation teams to deliver high‑quality, reusable IPs for next‑generation microcontrollers and microprocessors.

Responsibilities:

• Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off
• Define and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria
• Develop scalable, reusable UVM‑based verification environments for IP and subsystem verification
• Lead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metrics
• Apply AI/ML‑assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency
• Drive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verification
• Collaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration
• Review IP specifications and work with architects to translate requirements into robust verification plans and checkers
• Develop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors
• Work with EDA vendors to evaluate and adopt next‑generation verification, coverage, and analytics tools
• Mentor junior engineers and promote best‑in‑class verification practices and continuous improvement
• Support Gate‑Level Simulation (GLS), low‑power verification, and post‑silicon debug when required.
• Ensure IP deliverables meet quality, schedule, and reusability expectations for SoC integration.

Job Description:

We need an Firmware verification engineers who understand UFS/eMMC embedded NAND system design and firmware algorithms in order to create a firmware design verification plans and implement them in modern object oriented languages.

• Work closely with the system architects and the firmware team to develop design verification plans, test bench and test cases
• Develop an overall firmware validation strategy including defining validation infrastructure and validation methodology
• Debug the firmware and expose design issues
• Design functional tests required to meet customer needs
• Review SanDisk UFS/eMMC embedded NAND validation requirements and influence future SanDisk product design for debug and test
• Work with customers to understand field bugs and to enhance the validation coverage
• Interface with all key stakeholders to ensure product validation meets customer expectations and needs

Technical and analytical skills required

• Familiar with firmware development, Integration and validation
• Knowledgeable on product and quality standards and relevant host protocols, in particular eMMC and UFS.
• Test coverage methods for real-time embedded systems, especially storage systems and/or NAND storage
• Able to methodically root cause complex failure mechanism
• Strong programming knowledge & debugging skills in Python, C and C++.

• Soft skills, Excellent written and verbal skills, be a Team player
• Able to develop key relationships
• Able to elect requirements from all stakeholders
• Be able to work in pressure for quick resolution and delivery.

Job Description:

We need an Firmware verification engineers who understand UFS/eMMC embedded NAND system design and firmware algorithms in order to create a firmware design verification plans and implement them in modern object oriented languages.

• Work closely with the system architects and the firmware team to develop design verification plans, test bench and test cases
• Develop an overall firmware validation strategy including defining validation infrastructure and validation methodology
• Debug the firmware and expose design issues
• Design functional tests required to meet customer needs
• Review SanDisk UFS/eMMC embedded NAND validation requirements and influence future SanDisk product design for debug and test
• Work with customers to understand field bugs and to enhance the validation coverage
• Interface with all key stakeholders to ensure product validation meets customer expectations and needs

Technical and analytical skills required

• Familiar with firmware development, Integration and validation
• Knowledgeable on product and quality standards and relevant host protocols, in particular eMMC and UFS.
• Test coverage methods for real-time embedded systems, especially storage systems and/or NAND storage
• Able to methodically root cause complex failure mechanism
• Strong programming knowledge & debugging skills in Python, C and C++.

• Soft skills, Excellent written and verbal skills, be a Team player
• Able to develop key relationships
• Able to elect requirements from all stakeholders
• Be able to work in pressure for quick resolution and delivery.

• Roles & Responsibilities :
  The candidate will be part of the “Communication Protocol and HW ” team in MBRDI

• The candidate should be able to work with product database tool to evaluate HW specification of the ECUs

• Electronics component identification and understanding component specification

• The candidate has to understand the Mercedes standard specification and network architecture w.r.t physical layer parameter

• Candidate has to interact with the ECU responsible person and supplier.

   

• Transceiver recommendation and alternate part suggestion.

• Understanding electronic component datasheet and test reports analysis

• Understanding of the schematic architecture and electronic circuits review from the schematics
   

Do you want to be a part of revolutionizing the financial platforms that power LinkedIn? Are you interested in building software that will directly contribute to managing and optimizing financial operations for LinkedIn's business? Look no further. 

We're looking for a Senior Staff Software Engineer to join the Finance Engineering team to build the Next Gen Financial Platform. As a Senior Staff Software Engineer, you will be a key technical leader and role model within the team. We are looking for someone who designs and develops technology to serve business and technology objectives, aligns points of view across teams, and makes smart trade-offs to help achieve the goals of individual teams as well as LinkedIn's broader goals. You will be responsible for establishing design patterns and building the foundation/platform and enterprise applications that will power the financial ecosystem. You will architect and scale financial systems, implementing critical business processes while delivering secure distributed transactions across multiple data centers and ensuring compliance with SOX, PCI, GDPR. In this role, you'll have a unique opportunity to develop the software ecosystem that powers every financial transaction at LinkedIn. 

This role will be based in Bangalore, India. 

At LinkedIn, our approach to flexible work is centered on trust and optimized for culture, connection, clarity, and the evolving needs of our business. The work location of this role is hybrid, meaning it will be performed both from home and from a LinkedIn office on select days, as determined by the business needs of the team. 

Responsibilities 

• Provide architectural guidance and mentorship to up-level the engineering organization. 

• Actively improve the level of craftsmanship at LinkedIn by developing best practices and defining strategies. 

• Scale distributed applications, make architectural trade-offs by applying synchronous and asynchronous design patterns, write code, and deliver with speed and quality. 

• Produce high-quality software that is unit tested, code reviewed, and checked in regularly for continuous integration. 

• Be a role model and professional coach for engineers with a strong bias for action and a focus on craftsmanship. 

• Identify, leverage, and successfully evangelize opportunities; collaborate with cross-functional teams to design and build scalable platforms/products/services/tools; and improve engineering productivity across the organization. 

• Work with peers across teams to support and leverage a shared technical stack. 

• Resolve conflicts between teams within the organization to drive alignment and strengthen team culture. 

• Review others' work and share knowledge.