Total 6 job vacancies by Sventl Asia Pacific Pte. Ltd.

Responsibilities/Job Scope:

• Pre-silicon verification and post-silicon system validation

• Test case and test automation scripts development and test plan execution

• Debug system (hardware, software and firmware), provide expert support to internal as well as external customer

• Silicon characterization and failure analysis

• Booting and other source code development

• Interoperability Testing (IOP), debugging and propose solutions

• Requires interfaces with Architecture, Design, and Pre-silicon Validation teams in improving post-silicon test content and providing feedback for future on-die debug features

Qualifications and Experience:

• Bachelor’s degree and above of computer science or electronic and electric engineering or embedded system

• Minimum three years’ experience of hardware, firmware development and system verification in consumer/electronics products

• Familiar with system board design/debugging and usage of lab equipment like Oscilloscope and Logic analyzer

• Experience of silicon verification and test plan execution

• Understand Ethernet GPHY, Ethernet Switch/PCI/USB/PCI-E/ /SGMII/SPI bus protocol

• Experience of C/C++ and Python Programming language

• Knowledge of physical layer components such ADC, DAC, AGC, DSP, filtering, line driver, differential signals

• System Debug tools JTAG, EJTAG. Knowledge of Spirent Test center and scripting

• Team player, very proactive and self-motivated

Job Description & Requirements

• Netlist to GDSII at block level, Subsystem Level and at Full chip.
• Worked on multiple tapeouts on Netlist to GDSII
• Hierarchical partitioning and budgeting of block-level subsystems.
• Implementation of high performance (HP) cores, low power designs
• Node experience upto 7nm, 10nm, 14nm, 28nm.
• Timing Signoff in loop through STA and ECO cycle at block and at interface.
• Block level floor planning, power planning and IR drop analysis.
• Scan chain reordering / Scan Chain repartitioning
• CTS expertise and clock tree constraints creation for meeting specifications
• MMMC optimization at Block and Sub-System Level
• Timing closure with Crosstalk and AOCV / POCV
• TCL scripting to fundamentally understand tool usage.

MANDATORY EDA SKILLS

• PnR tools such as Synopsys ICC/ICC2 and/or Cadence Innovus

Job Description & Requirements

Bachelor / Master’s degree in electrical & Electronic Engineering with at least 3 years of relevant experience in leading successful CMOS IC Test development projects.

• Experience in Advantest 93K tester (should be familiar with SMT 7 & 8) or J750

• Smartest 7 or 8 hands-on experience.

• Multiple years of experience on the V93k platform/J750

• Responsible for preparing the Production Test packages (Hardware and Software), and

• Qualification Test programs

• Ensure Timely transfer of Engineering and Production test packages for Wafersort and Final

• (Packaged) Test to various test sites

• Support SoC Test/Test Program Integrators on day to day debug and analysis as required

• based on schedule Test Program Roadmap

• Support test program buyoff 1st line support as needed inclusive of troubleshooting and

• resolutions

• Strong 93k DC testing experience

• Knowledge on Programming concepts and C/C++, Python, Java/ VBA language – preferred

Netlist to GDSII at block level, Subsystem Level and at Full chip.

• Worked on multiple tapeouts on Netlist to GDSII

• Hierarchical partitioning and budgeting of block-level subsystems.

• Implementation of high performance (HP) cores, low power designs

• Node experience upto 7nm, 10nm, 14nm, 28nm.

• Timing Signoff in loop through STA and ECO cycle at block and at interface.

• Block level floor planning, power planning and IR drop analysis.

• Scan chain reordering / Scan Chain repartitioning

• CTS expertise and clock tree constraints creation for meeting specifications

• MMMC optimization at Block and Sub-System Level

• Timing closure with Crosstalk and AOCV / POCV

• TCL scripting to fundamentally understand tool usage.

MANDATORY EDA SKILLS

• PnR tools such as Synopsys ICC/ICC2 and/or Cadence Innovus

Job Description & Requirements

• Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level
• Develop IP level/SoC level test plans based on the design/architectural specs.
• Coverage Analysis and Coding
• Run simulations & regressions, debug test failures to identify test case issues & RTL design issues
• Define and develop block/full chip level verification environment and its components

Required Skills:

• 3–9 & above years of experience in ASIC Verification and Methodologies
• Good knowledge of System Verilog, SV-OVM/SV-UVM Methodologies
• Good understanding of RTL concepts
• Good understanding of AHB/AXI protocol
• Expertise in PCI-e/ USB/ Ethernet
• Need Experience on protocols MAC, FEC, and Serdes
• Knowledge of Perl/TCL is Must
• Good communication skill

Job Description & Requirements

Bachelor / Master’s degree in electrical & Electronic Engineering with at least 3 years of relevant experience in leading successful CMOS IC Test development projects.

• Experience in Advantest 93K tester (should be familiar with SMT 7 & 8) or J750

• Smartest 7 or 8 hands-on experience.

• Multiple years of experience on the V93k platform/J750

• Responsible for preparing the Production Test packages (Hardware and Software), and

• Qualification Test programs

• Ensure Timely transfer of Engineering and Production test packages for Wafersort and Final

• (Packaged) Test to various test sites

• Support SoC Test/Test Program Integrators on day to day debug and analysis as required

• based on schedule Test Program Roadmap

• Support test program buyoff 1st line support as needed inclusive of troubleshooting and

• resolutions

• Strong 93k DC testing experience

• Knowledge on Programming concepts and C/C++, Python, Java/ VBA language – preferred