Total 2 job vacancies by Starfive International Pte. Ltd.

Role Overview

You will be responsible for defining the next generation of high-performance, energy-efficient processor cores. You will bridge the gap between architectural intent and RTL implementation, driving the ISA extensions and microarchitectural features that differentiate our silicon. This role requires a deep understanding of pipeline design, memory hierarchy, and the evolving RISC-V ecosystem.

Key Responsibilities

• Microarchitecture Definition: Define and document detailed microarchitectural specifications for high-performance RISC-V cores, including fetch units, branch predictors, execution units, and complex memory subsystems.
• Performance Modelling: Develop and maintain performance models in C/C++ to explore microarchitecture impact on CPU performance.
• Performance Analysis: Utilize techniques like RTL simulation, performance modelling, hardware performance monitor (HPM) to identify bottlenecks in the pipeline and suggest architectural improvements.
• ISA Extension & Customization: Propose microarchitecture design for standard RISC-V ISA extension (e.g. Vector, Crypto, Bitmanip) and for customized instructions to meet the needs of customers.

Required Technical Skills

• Instruction Set Architecture (ISA): Knowledge of the RISC-V ISA and experience with privilege levels (Machine, Supervisor, User). Knowledge of ARM Aarch ISA is a plus.
• CPU Microarchitecture: Deep understanding of modern CPU techniques: out-of-order execution, register renaming, superscalar pipelines, and speculative execution.
• Modeling & Languages:
• Deep experience with C/C++
• Scripting proficiency in Python or Bash for automation and data analysis.

Preferred Skills and Experiences

• AI-Assisted Workflow: Experience with LLM-assisted coding (vibe coding) and/or AI-agent-assisted workflow automation.
• Linux OS: Deep understanding of Linux system calls. Experiences with Linux kernel modules or device drivers.
• Low-level Systems: Experience with Linux kernel boot flow on RISC-V or firmware development (OpenSBI/U-Boot).
• Verilog/System Verilog: Experience in RTL development with Verilog/System Verilog.

Education & Experience

• BS/MS or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• Work experience of CPU architect or RTL designer is a plus.

Role Overview

You will be responsible for defining the next generation of high-performance, energy-efficient processor cores. You will bridge the gap between architectural intent and RTL implementation, driving the ISA extensions and microarchitectural features that differentiate our silicon. This role requires a deep understanding of pipeline design, memory hierarchy, and the evolving RISC-V ecosystem.

Key Responsibilities

• Microarchitecture Definition: Define and document detailed microarchitectural specifications for high-performance RISC-V cores, including fetch units, branch predictors, execution units, and complex memory subsystems.
• Performance Modelling: Develop and maintain performance models in C/C++ to explore microarchitecture impact on CPU performance.
• Performance Analysis: Utilize techniques like RTL simulation, performance modelling, hardware performance monitor (HPM) to identify bottlenecks in the pipeline and suggest architectural improvements.
• ISA Extension & Customization: Propose microarchitecture design for standard RISC-V ISA extension (e.g. Vector, Crypto, Bitmanip) and for customized instructions to meet the needs of customers.

Required Technical Skills

• Instruction Set Architecture (ISA): Knowledge of the RISC-V ISA and experience with privilege levels (Machine, Supervisor, User). Knowledge of ARM Aarch ISA is a plus.
• CPU Microarchitecture: Deep understanding of modern CPU techniques: out-of-order execution, register renaming, superscalar pipelines, and speculative execution.
• Modeling & Languages:
• Deep experience with C/C++
• Scripting proficiency in Python or Bash for automation and data analysis.

Preferred Skills and Experiences

• AI-Assisted Workflow: Experience with LLM-assisted coding (vibe coding) and/or AI-agent-assisted workflow automation.
• Linux OS: Deep understanding of Linux system calls. Experiences with Linux kernel modules or device drivers.
• Low-level Systems: Experience with Linux kernel boot flow on RISC-V or firmware development (OpenSBI/U-Boot).
• Verilog/System Verilog: Experience in RTL development with Verilog/System Verilog.

Education & Experience

• BS/MS or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• Work experience of CPU architect or RTL designer is a plus.