Total 3 job vacancies by Serdesworks Pte. Ltd.

About SerdesWorks Pte. Ltd.

SerdesWorks is a deep-tech semiconductor startup focused on developing high-speed SerDes PHY IP and IO die solutions for next-generation interfaces including DDR5, MIPI, PCIe, and UCIe.

We are building advanced PHY solutions in TSMC 22nm / 12nm and beyond, targeting high-performance computing, AI accelerators, and chiplet-based systems.

Role Overview

We are seeking a Senior Analog Layout Engineer with strong experience in advanced process nodes and high-speed SerDes PHY design to drive full-custom layout implementation of high-performance analog/mixed-signal circuits.

This role is critical in ensuring silicon success, signal integrity, and manufacturability of our next-generation IP.

Key Responsibilities

• Perform full-custom layout design for high-speed analog/mixed-signal blocks, including:
• PLL / CDRTX/RX front-end (driver, CTLE, DFE)Clocking and bias circuits
• Execute layout in advanced nodes (≤22nm, e.g. 22nm / 12nm / 6nm)
• Ensure layout quality through:
• DRC / LVS / ERC closureEM/IR and reliability checksParasitic extraction (PEX) and post-layout optimization
• Apply high-speed layout techniques, including:
• Matching, shielding, symmetryLow parasitic routing for multi-Gbps signalsCrosstalk and substrate noise mitigation
• Collaborate closely with:
• Analog designers (schematic and simulation alignment)Digital/RTL teams (integration with PCS)Packaging teams (IO bumping, IO die considerations)
• Support tape-out activities and silicon bring-up readiness

Requirements

Must-Have:

• Diploma or Bachelor’s degree in Electrical/Electronic Engineering
• ≥3 years of experience in custom IC layout design
• Proven experience in advanced nodes (≤28nm, preferably 22nm/12nm FinFET/FD-SOI)High-speed SerDes or RF/analog circuits
• Strong knowledge of layout matching techniques (common centroid, interdigitation)Parasitic effects in high-speed designs
• Hands-on experience with Synopsys Custom Compiler or Cadence Virtuoso (Layout XL / GXL)DRC/LVS tools (Mentor Calibre or equivalent)

Good-to-Have:

1. Experience in multi-Gbps SerDes PHY (>5Gbps)
2. Familiarity with transmission line effects and impedance control
3. ESD design and IO layout
4. Advanced packaging (flip-chip, chiplet, UCIe)
5. Experience with EM/IR tools and reliability analysis
6. Prior tape-out experience in advanced nodes

Why Join Us

• Work on cutting-edge SerDes and chiplet IO technologies
• Opportunity to contribute to first-silicon success in advanced nodes
• Fast-paced startup environment with strong technical ownership
• Exposure to end-to-end PHY development (architecture → silicon)
• Opportunity to participate in global semiconductor ecosystem expansion

Company Overview

SerDesWorks Pte Ltd is located in Singapore, specializing in proprietary semiconductor IP development and advanced SerDes PHY design for international markets, focusing on high-speed, deep-tech solutions and engineering productivity improvements.

Job Summary

This role strengthens SerDesWorks’ engineering capabilities in high-speed SerDes PHY development, supporting advanced node designs and international market expansion with competitive PHY solutions.

Responsibilities

• Design and develop PLL, CDR, and CTLE circuits to support high-speed SerDes PHY functionality.
• Implement and optimize high-speed transmitter (TX) and receiver (RX) circuits operating above 5 Gbps to meet performance targets.
• Analyze jitter and signal integrity to ensure robust data transmission and system reliability.
• Apply equalization techniques including CTLE, DFE, and FFE to enhance signal quality in high-speed communication channels.
• Utilize CMOS analog design fundamentals to create efficient and scalable analog circuit components.
• Operate Cadence Virtuoso or Synopsys Custom Compiler environments to perform custom IC design and layout tasks.
• Conduct circuit simulations and verification using HSPICE and PrimeSim to validate design performance.
• Develop scripts and tools in MATLAB or Python to automate design processes and improve engineering productivity.

About Us

SerdesWorks is a deep-tech semiconductor startup focused on developing high-performance SerDes and interface IP solutions for next-generation data communication systems, including PCIe, UCIe, MIPI, DDR, and high-speed chiplet interconnects.

We are building advanced PHY and digital subsystems in TSMC advanced nodes (22nm / 12nm and beyond), targeting applications in AI compute, data centers, storage, and mobile platforms.

Role Overview

We are seeking a highly motivated RTL / Digital Design Engineer to develop and implement high-speed interface digital subsystems (PCS / controller logic) for SerDes and PHY IP.

You will work closely with analog designers, system architects, and verification engineers to deliver production-quality IP.

Key Responsibilities

1. RTL Design & Architecture

Design and implement RTL for PHY PCS (Physical Coding Sublayer) and digital control blocks

Develop modules for:

- Encoding/decoding (e.g., 8b/10b, 128b/130b, 256b/257b)

- Lane alignment and deskew

- Elastic buffers and clock domain crossing (CDC)

- Link training and state machines (e.g., LTSSM for PCIe, MIPI state machines)

- Translate system-level specifications into synthesizable Verilog/SystemVerilog

2. Integration with Analog PHY

Interface digital logic with analog front-end (PLL, CDR, TX/RX, CTLE)

Define and implement:

- Digital-analog control interfaces

- Calibration and adaptation loops

- Support mixed-signal simulation (AMS co-sim)

3. Verification & Validation

Collaborate with verification team on:

- Testbench development (UVM preferred)

- Functional coverage and corner-case validation

Perform:

- RTL simulation (VCS/Xcelium)

- Lint, CDC, and reset domain checks

- Debug functional and timing issues

4. Synthesis & Implementation Support

Ensure RTL is optimized for:

- High frequency (multi-GHz operation)

- Low latency and power efficiency

Work with backend team on:

- Timing closure

- Area/power trade-offs

5. Compliance & Standards

Implement designs compliant with:

- PCIe Gen5/Gen6

- MIPI C-PHY / D-PHY / M-PHY

- UCIe / DDR interfaces

- Participate in compliance verification and interoperability testing

Requirements

Bachelor’s / Master’s in Electrical Engineering / Computer Engineering

≥ 3 years experience in digital IC / RTL design

Strong proficiency in:

- Verilog / System-Verilog

- Digital design fundamentals (FSM, CDC, pipelining, timing)

Experience with:

- RTL simulation tools (Synopsys VCS / Cadence Xcelium)

- Lint and CDC tools (SpyGlass / Jasper / Questa CDC)

Preferred (Strong Advantage)

Experience in high-speed interface / SerDes / PHY design

Knowledge of:

- PCIe / MIPI / DDR / Ethernet protocols

Familiarity with:

- UVM verification methodology

- Synthesis tools (Design Compiler / Genus)

Understanding of:

- Clocking architectures (PLL/CDR interaction)

- Low-power design techniques