Total 6 job vacancies by Ethos Tech One Pte. Ltd.

Job Descriptions

• Develop and Review Test Plan based on IC design specification
• Develop constrained-Random verification environment for complex DUT
• Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance
• Implement coverage matrix using cover point and assertion
• Create and debug tests for DUT
• Resolve bugs with remote designers

Requirements

• Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with min 1 year of experience
• Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM
• Strong understanding of verification process from test plan to coverage completion
• Strong communication and Analytical skills
• Understanding of HDL (Verilog, VHDL)
• Experience in using leading EDA software tools like Cadence/ Synopsys

Job Description

• Design and Develop ICs using leading EDA software; work on RTL to GDS, including synthesis, layout, floor planning, placement, clock tree insertion and routing.
• Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc.
• Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
• Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products.

Job Requirements

• Bachelor/Masters Degree in Electronics/Electrical/Computer Engineering with min 1 year experience
• Good experience and knowledge in design flow from Netlist to GDS, Synthesis, layout, Floor Planning, route , STA, CTS, RC Extraction and correlation
• Static timing analysis, power and noise analysis and back-end verification across multiple projects.
• Proficient with backend design EDA tools, Synopsys ICC2 preferred
• Successfully track records of taping out complex SOC
• Working knowledge of deep sub-micron routing issues as they relate to power and timing.
• Proficiency using Perl and TCL
• Self-motivated team worker, good verbal and written communication skills

Key responsibilities:

• Work closely with design team and make sure DFT structures are correctly inserted.
• Responsible for developing, implementing and verifying DFT schemes on hard-IPs in FPGAs.
• Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault model
• Responsible for debugging of scan/mbist pattern issues on bench/ATE to root cause the problem
• Assist in Diagnosis and Yield enhancement through product lifecycle

Qualifications:

• BS or MS in Electrical/Electronic/Computer Engineering with 1 or more year DFT experience
• Experience in creating and implementing complex chip-level DFT architecture
• Experience in DFT implementation including Scan and Scan Compression at IP and SoC level
• Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.
• Proficient in logic design using Verilog and experience in synthesis and STA
• Experience in developing test benches and simulation in RTL/GATE/SDF environments
• Knowledge of MBIST is a plus.
• Knowledge of FPGA synthesis and design flow is a plus
• Experience with post-silicon debug and bench setup is a plus
• Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, Python etc
• Good communication skills, self-motivated, works well in a group environment that spans across continents

Job Descriptions

• Responsible for IP / sub-system level digital design development, RTL coding and implementation
• Design and development with leading edge technology nodes on digital logic blocks
• DFT implementation and verification.
• Perform test bench development and functional verification of developed digital logic blocks.
• Perform post silicon validation, testing and debug of block functionality on prototype silicon.
• Work closely with stakeholders to develop design specifications documents, verification plans, and validation test plans.

Job Requirements:

• Bachelor/Master Degree in Electronics Engineering or equivalent
• 1 year or more related experience in ASIC/digital IC development with completion of complex ASIC or IC tapeouts.
• Working experience of RTL coding in Verilog/VHDL language, verification, logic synthesis and DFT in high performance design.
• Experience in test planning/creation/analysis of DFT/ATPG scan and silicon validation.
• Excellent communication skill and team player
• Knowledge of UVM is an advantage.

Job Description

• Design and Develop ICs using leading EDA software; work on RTL to GDS, including synthesis, layout, floor planning, placement, clock tree insertion and routing.
• Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc.
• Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
• Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products.

Job Requirements

• Bachelor/Masters Degree in Electronics/Electrical/Computer Engineering with min 1 year experience
• Good experience and knowledge in design flow from Netlist to GDS, Synthesis, layout, Floor Planning, route , STA, CTS, RC Extraction and correlation
• Static timing analysis, power and noise analysis and back-end verification across multiple projects.
• Proficient with backend design EDA tools, Synopsys ICC2 preferred
• Successfully track records of taping out complex SOC
• Working knowledge of deep sub-micron routing issues as they relate to power and timing.
• Proficiency using Perl and TCL
• Self-motivated team worker, good verbal and written communication skills

Job Descriptions

• Develop and Review Test Plan based on IC design specification
• Develop constrained-Random verification environment for complex DUT
• Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance
• Implement coverage matrix using cover point and assertion
• Create and debug tests for DUT
• Resolve bugs with remote designers

Requirements

• Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with min 1 year of experience
• Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM
• Strong understanding of verification process from test plan to coverage completion
• Strong communication and Analytical skills
• Understanding of HDL (Verilog, VHDL)
• Experience in using leading EDA software tools like Cadence/ Synopsys