Total 10 job vacancies by Xilinx Asia Pacific Pte. Ltd.

THE ROLE:

You will be highly driven and leading complex, cross-functional programs that enable successful product launches and manufacturing execution. You will be at the center of semiconductor product lifecycle execution, from new product introduction (NPI) through production ramp. You will partner with engineering, operations, supply chain, and external partners to translate strategy into action, ensuring programs are delivered on schedule and with high quality. Success in this position will be measured by your ability to deliver program objectives and products on time, within scope, and to the highest standards of quality. You will be working in a dynamic, fast-paced environment where you will influence decision-making, solve complex challenges, and drive alignment across global teams. You will gain deep exposure to semiconductor manufacturing, product development, and operations while working on cutting-edge technologies and product launches.

THE PERSON:

You will be proactive, structured, and result-oriented individual who thrives in complex and fast-moving environments.

You are:

• A strong communicator who can influence and align stakeholders across organizational boundaries
• A self-starter who operates with independence and takes ownership of outcomes
• Comfortable navigating ambiguity and managing competing priorities
• Analytical and detail-oriented, with the ability to connect the big picture to execution
• Collaborative and capable of motivating cross-functional teams toward shared goals
• Resilient under pressure, with a continuous improvement mindset
• Resourceful, adaptable, and driven to deliver high-impact results

KEY RESPONSIBILITIES:

• Lead and coordinate end-to-end program schedules to support product releases and manufacturing readiness
• Drive New Product Introduction (NPI) execution based on Plan-of-Record, covering phases from tape-out through qualification and production release
• Manage cross-functional alignment across engineering, operations, supply chain, business units and external partners
• Proactively identify and mitigate risks, dependencies, and issues to keep programs on track
• Oversee engineering sample execution and readiness for silicon bring-up activities
• Coordinate programs involving external manufacturing sites for their qualification, production readiness, capacity setup, and production control
• Drive Product Lifecycle Management, including milestone tracking, gate reviews, and change management
• Ensure effective communication and governance through structured updates, stakeholder syncs, and escalation management
• Enable operational excellence by driving efficient, scalable manufacturing solutions across the product lifecycle
• Empower functional teams to meet program goals and deliver integrated outcomes
• Own end-to-end program delivery, optimize processes, and contribute to strategic planning and continuous improvement

PREFERRED EXPERIENCE:

• Good experience in semiconductor engineering, manufacturing, or supply chain environments, preferably in program management
• Good understanding of semiconductor product lifecycle, including wafer fabrication, test, qualification, and manufacturing operations
• Exposure to areas such as foundry engineering, product/test engineering, silicon verification, characterization, package & assembly, and product qualification
• Demonstrated ability to drive complex, cross-functional programs and deliver results
• Experience working across multiple sites and within global, multicultural teams
• Proficiency in program management tools and techniques for planning, monitoring, and control
• Strong stakeholder management and cross-functional collaboration skills
• Proficiency in Microsoft Excel, PowerPoint, and collaboration tools

ACADEMIC CREDENTIALS:

• Bachelor’s degree in Engineering or Supply Chain related fields preferred
• Certifications in Program or Project Management (e.g., PMP, Agile) desired

LOCATION:

Singapore

THE ROLE:

DFT engineer will lead strong engineering team on Scan, MBIST, iJTAG test development of latest AMD products. The IPs range from complex processors, AI computation blocks, to state-of-the-art controller IPs which provide automotive, data center, machine learning and high-speed communication solutions. You will work closely with designers to make sure DFT structures are correctly implemented, with test engineers to make sure ATE test programs can be generated from the DFT (ATPG, MBIST) tools, with product engineers to make sure scan/MBIST production test can run seamlessly and stable, and with yield engineers to debug and root-cause failures/defects. You will get the opportunity to expand technical knowledge beyond DFT into embedded processor firmware, complex chip simulation, RTL implementation for ASIC & FPGA and deep silicon debug works all the way to high-volume production requirement. This is the role to oversee complete silicon cycle from design to production phases.

THE PERSON:

We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful Member of Technical Staff DFT engineer will interact with many external teams and must confidently represent his/her organization.

KEY RESPONSIBILITIES:

• Manage DFT engineers resolving technical challenges and meeting product schedule
• The role is in AMD global quality and operation organization driving best manufacturing test solution through pre and post silicon activities
• Work closely with design teams and make sure DFT structures are correctly implemented.
• Responsible for developing, implementing and verifying DFT schemes on hard-IPs in AMD ASIC and FPGA products.
• Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault models
• Responsible for testing other parts of the design, including memory, mixed-signal, I/Os, custom LBISTs & MBISTs, IEEE1149.1 JTAG and IEEE1687 IJTAG
• Responsible to develop Firmware driven cost-effective test strategies/methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench/ATE
• Collaborate closely with the New Product Introduction and Test/Product teams to ensure timely delivery of robust test patterns, and manage debugging of pattern issues on bench/ATE to root cause the problem
• Assist in Diagnosis and Yield enhancement through product lifecycle
• Develop an adaptive and cohesive team to take up any challenging tasks entrusted by management

PREFERRED EXPERIENCE:

• Experience DFT engineering experience through DFT pre and post silicon cycles
• Experience in creating and implementing complex chip-level DFT architecture
• Experience in DFT implementation including Scan and Scan Compression at IP and SoC level
• Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.
• Strong MBIST knowledge
• Knowledge of Tessent Streaming Scan Network SSN and hand-on experience is a big plus
• Proficient in logic design using Verilog and experience in synthesis and STA
• Experience in developing test benches and simulation in RTL/GATE/SDF environments
• Knowledge of FPGA synthesis and design flow is a plus
• Experience with post-silicon debug and bench equipment (e.g., oscilloscope and logic analyser)
• Good communication skills, works well in a group environment that spans across continents
• Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc

ACADEMIC CREDENTIALS:

• MS or Ph.D. in Electrical/Electronic/Computer Engineering

THE ROLE:

You will be responsible for testing, validating, and optimizing optical transceivers to ensure high performance and reliability in fiber optic communication systems. This role involves working closely with design teams to develop validation methodologies and improve product quality.

THE PERSON

You are a detail-oriented engineer with a strong foundation in optical communication systems and a passion for innovation. You thrive in collaborative environments and are driven to solve complex technical challenges. Your hands-on experience with optical components and high-speed link validation makes you a valuable contributor to our cutting-edge silicon design team.

KEY RESPONSIBILITIES:

• You will develop and execute validation plans for optical transceivers and related components.
• Perform calibration, characterization, and testing of electro-optic transceivers.
• Set up and maintain automated test platforms for optical transceiver validation.
• Analyze test results and troubleshoot performance issues.
• Collaborate with cross-functional teams to improve product design and reliability.
• Document validation processes and generate technical reports.
• Stay updated with industry trends and advancements in optical communication technologies.

PREFERRED EXPERIENCE:

• Hands on optical components testing and high-speed links validation experiences. 
• Technical Skills: Strong knowledge of optical communication systems and fiber optics.
• Experience with Python, C, MATLAB, and data analysis.
• Ability to debug and validate hardware/electronics.
• Soft Skills: Strong analytical and problem-solving abilities.
• Excellent communication and teamwork skills.
• Experience with Silicon Photonics and high-speed optical interconnects.
• Knowledge of optical packaging and characterization techniques.

ACADEMIC CREDENTIALS:

• Bachelor's/Master’s/Ph.D. in Electrical Engineering, Optical Communications, or related fields.

LOCATION:

Singapore

THE ROLE:

As a senior staff member of the product characterization team, you will evaluate the performance of AMD AECG products, develop, lead and characterize the next generation Memory Controller IPs.

THE PERSON:

• Strongly motivated individual from post-silicon validation background.
• Excellent communication and presentation skills, demonstrated through technical publications, presentations, training, executive briefings, etc.
• Adept at collaboration and mentorship skills to train and guide fellow engineers and elevate the skills of the team around you.

KEY RESPONSIBILITIES:

• Gain expertise into the AMD SoC architecture to characterize next generation Memory Subsystem (Controller, PHY and IO) for various supported protocols such as DDR4, LPDDR4, DDR5, LPDDR5, DDR6 and LPDDR6.
• Understand Pattern development nuances and guide the team for bench data collection and debug with lab instruments when necessary.
• Work closely with cross functional teams from design and firmware side to identify key new features, firmware stability and ensure proper test coverage for the same.
• Drive continuous improvement initiatives on automated test scripts and test frameworks for efficient data collection, test-time optimization and data analysis.
• Stay updated with the latest developments in Memory specifications and trends to inform product strategy and direction
• Statistical data analysis to post process volume results for data correlation across Process corners and outlier analysis.
• Responsible for isolating the issue to a specific area such as test gaps, SW bug, silicon bug, or process deviation using bench setup and instill good debug practices in the team.
• Drive cross-functional discussions to address the issues uncovered from debugs and collaborate for ensuring screens are in-place for gaps identified.

PREFERRED EXPERIENCE:

• Extensive years of experience into post-silicon validation with strong background on SoC validation and system level testing.
• Technical leadership experience leading a small group of senior engineers.
• Strong understanding of ARM SoC architecture and Memory protocols such as DDR5 and LPDDR5.
• Experienced on bench testing and debug skills with lab instruments usage.
• Proficiency in using test equipment such as oscilloscopes, logic analyzers and protocol analyzers.
• Experienced in Linux environment, data analysis and scripting languages (e.g. Python, Perl) for automation and data processing.
• Strong communication and leadership skills, including data presentation and ability to work well in a group environment that spans across continents.
• Experience with AMD/Xilinx Vivado and FPGA design flow is a plus.

ACADEMIC CREDENTIALS:

• BS in EE, CS, ECE or related field; MS preferred.

THE ROLE:

AMD is seeking a talented, motivated and self-driven digital design engineer to be part of the SerDes Technology group. You will be part of the team developing SerDes/Transceiver designs and solutions. The role involves work on all aspects of the FPGA/ASIC digital design flow including architectural specification, test planning, RTL design, functional verification, through synthesis and implementation to hardware and post silicon validation.

THE PERSON:

The successful candidate will execute digital design work and contribute technically with a high general impact on the overall design. We are seeking a team player who is innovative, highly accurate and detail-oriented, willing to learn, and possessing excellent communication and problem-solving skills to join our design team.

KEY RESPONSIBILITIES:

• Design and development with leading edge technology nodes on digital logic blocks.
• DFT implementation and verification.
• Perform test bench development and functional verification of developed digital logic blocks.
• Perform post silicon validation, testing and debug of block functionality on prototype silicon.
• Work closely with system architect, project manager, design and verification teams to develop design specifications documents, verification plans, and validation test plans.

PREFERRED EXPERIENCE:

• Experience in ASIC or digital IC design, with hands‑on involvement in RTL development (Verilog/SystemVerilog) for complex digital blocks or subsystems.
• Exposure to the front‑end digital design flow, including RTL coding, functional verification, lint/CDC checks, logic synthesis, and timing analysis.
• Experience contributing to one or more ASIC or FPGA tapeouts, either at block or subsystem level.
• Familiarity with DFT concepts and flows; hands‑on experience is a plus but not mandatory.
• Exposure to post‑silicon validation, testing, or debug, with an interest in understanding silicon behaviour and root‑cause analysis.
• Background in high‑performance or high‑speed digital designs (e.g., SoC interconnects, memory interfaces, I/O subsystems, data‑path logic) is advantageous.
• Knowledge of SystemVerilog and UVM is a plus.
• Strong problem‑solving skills, willingness to learn new domains (e.g., SerDes/transceiver logic), and ability to collaborate effectively with cross‑functional teams.

ACADEMIC CREDENTIALS:

• Bachelor or Masters Degree in Electronic Engineering.

LOCATION:

Singapore

THE ROLE:

AMD is seeking a talented, motivated and self-driven digital design engineer to be part of the SerDes Technology group. You will be part of the team developing SerDes/Transceiver designs and solutions. The role involves work on all aspects of the FPGA/ASIC digital design flow including architectural specification, test planning, RTL design, functional verification, through synthesis and implementation to hardware and post silicon validation.

THE PERSON:

The successful candidate will execute digital design work and contribute technically with a high general impact on the overall design. We are seeking a team player who is innovative, highly accurate and detail-oriented, willing to learn, and possessing excellent communication and problem-solving skills to join our design team.

KEY RESPONSIBILITIES:

• Design and development with leading edge technology nodes on digital logic blocks.
• DFT implementation and verification.
• Perform test bench development and functional verification of developed digital logic blocks.
• Perform post silicon validation, testing and debug of block functionality on prototype silicon.
• Work closely with system architect, project manager, design and verification teams to develop design specifications documents, verification plans, and validation test plans.

PREFERRED EXPERIENCE:

• Experience in ASIC or digital IC design, with hands‑on involvement in RTL development (Verilog/SystemVerilog) for complex digital blocks or subsystems.
• Exposure to the front‑end digital design flow, including RTL coding, functional verification, lint/CDC checks, logic synthesis, and timing analysis.
• Experience contributing to one or more ASIC or FPGA tapeouts, either at block or subsystem level.
• Familiarity with DFT concepts and flows; hands‑on experience is a plus but not mandatory.
• Exposure to post‑silicon validation, testing, or debug, with an interest in understanding silicon behaviour and root‑cause analysis.
• Background in high‑performance or high‑speed digital designs (e.g., SoC interconnects, memory interfaces, I/O subsystems, data‑path logic) is advantageous.
• Knowledge of SystemVerilog and UVM is a plus.
• Strong problem‑solving skills, willingness to learn new domains (e.g., SerDes/transceiver logic), and ability to collaborate effectively with cross‑functional teams.

ACADEMIC CREDENTIALS:

• Bachelor or Masters Degree in Electronic Engineering.

LOCATION:

Singapore

THE ROLE: 

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s SerDes IP, resulting in no bugs in the final design.   

THE PERSON:  

You have a passion for modern, complex SerDes architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

KEY RESPONSIBILITIES:  

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified 
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases 
• Estimate the time required to write the new feature tests and any required changes to the test environment 
• Build the directed and random verification tests 
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues  
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements 

PREFERRED EXPERIENCE:  

• Proficient in IP level ASIC verification 
• Proficient in debugging firmware and RTL code using simulation tools  
• Proficient in using UVM testbenches and working in Linux and Windows environments 
• Experienced with Verilog, System Verilog, C, and C++   
• Digital design, Analog Design, SerDes, PCIe and Ethernet knowledge 
• Developing UVM based verification frameworks and testbenches, processes and flows 
• Experienced with Co-Sim and UPI verification.
• Automating workflows in a distributed compute environment.   
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process 
• Strong background in the C++ language, preferably on Linux with exposure to Windows platform 
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language 
• Good working knowledge of SystemC and TLM with some related experience.   
• Scripting language experience: Perl, Python, Makefile, shell preferred.   
• Exposure to leadership or mentorship is an asset 
• Desirable assets with prior exposure to video codec system or other multimedia solutions.   
• Experienced with ChatGPT, MS-Copilot and other AI tools.

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

THE ROLE:

AMD is seeking a talented SerDes Verification Engineer to work on verifying and validating high‑speed interfaces used in advanced SoCs and chiplet designs. The role involves building UVM/SystemVerilog testbenches, running simulations, debugging timing and protocol issues, and evaluating signal integrity, jitter, BER, and eye diagrams. Close collaboration with design and hardware teams ensures compliance with protocols such as UCIe, PCIe, and DDR, delivering reliable, high‑performance silicon.

THE PERSON:

As a SerDes Verification Engineer, you will be responsible for the verification and validation of high-speed SerDes interfaces, including testing signal integrity, performance, and protocol compliance. You will work closely with hardware and design teams to ensure that SerDes designs meet the required specifications, operating parameters, and quality standards.

KEY RESPONSIBILITIES:

• Verification of SerDes Designs: Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements.
• Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL).
• Simulation and Debugging: Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks.
• Performance Evaluation: Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics.
• Protocol Compliance Testing: Verify adherence to relevant SerDes protocols such as UCIe, PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols.
• Automated Testing: Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations.
• Collaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes.
• Documentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing.
• Continuous Improvement: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies.

 PREFERRED EXPERIENCE:

• Experience in SerDes verification or high-speed communication verification.
• Strong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools.
• Knowledge of high-speed serial protocols such as UCIe, PCIe, Ethernet, USB, DDR, or custom protocols.
• Experience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams.
• Solid understanding of SerDes architectures, link training, and equalization.
• Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance).
• Familiarity with hardware description languages (HDL) like VHDL or Verilog.
• Strong analytical, problem-solving, and communication skills.
• Experience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification.
• Understanding of UCIe protocol and its role in chiplet-to-chiplet communication.
• Experience with Python, Perl, or similar scripting languages for automation.
• Exposure to high-speed memory interface design and verification, including DDR controller IP verification.
• Ability to work in a fast-paced environment and manage multiple verification tasks.

THE ROLE:

Test Engineering is a cost, quality, and time-to-market driven team responsible for enabling the availability of FPGAs, SoCs & ACAPs to our customers.  The Test Engineer will be involved in new product release as well as production yield/quality improvement activities.  This role requires close collaboration with Test Pattern Developers & Product Engineers to create test programs that provide optimum test coverage for our products.  There are also ample opportunities to work on cost reduction and test capacity improvement projects.    

THE PERSON:

Looks forward to new challenges. Has good analytical and problem-solving skills. Enjoy working in cross-functional teams. Has effective communication and presentation skills.

Fluent in both oral and written English.

KEY RESPONSIBILITIES:

• Develops ATE test programs to test FPGA & SoCs products.  This involves constructing or enhancing test methods, and integration of timings/ levels and test flow into a test program.
• Involved with New Product Introduction process and works with test pattern developers in generating, debugging, and implementing new test patterns.
• Other duties include working with product/yield engineers in implementing new test requirements for yield and quality improvements; as well as working on productivity improvement and cost reduction activities such as test time reduction and multi-site development & implementation.
• Analyze large test datasets to drive yield improvement, failure analysis, and continuous optimization; build automated dashboards and reports.
• Manage and execute complex test cost reduction projects and New Product bring up

PREFERRED EXPERIENCE:

• The candidate should have 5 or more years of ATE test program development experience. In-depth knowledge and hands-on experience in one or more of the following ATE platforms are desired: Advantest T2000 and/or Verigy93000 (Smartest 7/8).
• There should be a proven track record of developing and releasing new test programs to production.  Good understanding of test concepts & new product development cycle is desired.
• Advanced proficiency in Python and C++ for ATE test development, tooling, and data analysis; experienced with libraries such as OpenSSL, NumPy, and Pandas, and capable of designing and maintaining robust regression test suites.
• Practical experience with Git for version control and Confluence for documentation and knowledge management.
• Strong hands-on Linux skills for development, automation, scripting, and environment management.

ACADEMIC CREDENTIALS:

• Bachelor’s or master’s degree in Electronics Engineering
• Specialization in Electronics or Computer Engineering is preferred.

THE ROLE:

AMD is seeking a talented and self-driven digital design engineer to join the SerDes Technology group, where you will contribute directly to the architecture and implementation of next-generation high speed interface technologies. You will be part of the team developing SerDes/Transceiver designs and solutions. The role involves work on all aspects of the FPGA/ASIC digital design flow including architectural specification, test planning, RTL design, functional verification, through synthesis and implementation to hardware and post silicon validation.

THE PERSON:

You will execute design work and contribute technically with a high general impact on the overall design. We are seeking someone who is innovative, highly accurate and detail-oriented, possessing good communication and problem-solving skills to join our design team.

KEY RESPONSIBILITIES:

• Architecture, design, and development of complex digital logic blocks in leading edge technology nodes.
• DFT implementation and verification.
• Perform test bench development and functional verification of developed digital logic blocks.
• Perform post silicon validation, testing and debug of block functionality on prototype silicon.
• Work closely with system architect, project manager, design and verification teams to develop design specifications documents, verification plans, and validation test plans.

PREFERRED EXPERIENCE:

• Experience in ASIC/digital IC development with completion of several complex ASIC or IC production tapeouts.
• Proven experience across RTL design in Verilog/VHDL, functional verification, synthesis and DFT, applied to complex high performance design.
• Strong understanding of the end‑to‑end digital ASIC design flow, from RTL architecture through sign‑off methodologies.
• Excellent verbal and written communication skills. Strong interpersonal skills.
• Problem solving and debugging skills.
• Knowledge of UVM and SystemVerilog language.
• Experience using AI‑assisted tools to support engineering productivity and workflow efficiency.

ACADEMIC CREDENTIALS:

• Bachelor or Masters Degree in Electronic Engineering, with years relevant work experience.

LOCATION:

Singapore