Total 121 job vacancies by Renesas Electronics

Staff Engineer, Digital Design role requiring 8+ years of experience of Digital design in Analog Mixed signal ICs for developing Power Management ICs as part of 2.6B$ Power Business Unit at Renesas. Primary responsibilities include leading team which will fully own defining the microarchitecture to developing all Digital components of power management ICs, starting from System requirements. Due to the complex nature of Chips and significant Analog as well as Digital contents, collaboration with cross-functional teams to ensure successful integration of Digital and Analog components in ICs, is a must. The candidate will work on a wide range of exciting and cutting edge PMICs, including Linear and Switching DC-DC converters powering the next generation of most sought-after phones and handheld devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.

Essential Functions:

• Must have experience of defining Dig-Ana boundary and Digital design scope for Power Management ICs/Analog intensive ICs
• Must have experience of defining the micro-architectures and sub-blocks for the ICs to ensure optimized Digital design, RTL design and Gate level netlist etc.
• Must be aware of Power Sensitive digital design and doing Power estimation for the Digital I/Ps
• Must be able to handle Clock Domain Crossing across multiple clock domains seamlessly and in a glitch free manner.
• Should have experience of OTP, MTP, Efuse read/writes, controller design and data bus handling, Register read/write, Trimming of Analog parts/functions etc.
• Should be able to create Sequences (including Power UP/Down) and State Machines and Transitions to/from any state to another based on the IC requirements.
• Should be an expert of one or more Power Chip Communication I/Ps and protocols e.g. I2C, PMBUS, SVI3, SVID etc.
• Should be able to implement and analyse filters & feedback loops in Digital, conversant with Z-domain analysis.
• Must have done multiple silicon debugs, root cause analysis of issues, design to silicon correlation etc.
• Should understand commonly used control loop architectures (Constant Freq, Constant ON/OFF Time, Current mode etc) and pros/limitations of each.
• Must be able to bring in innovative ideas to improve designs to meet challenging specifications and achieve better system performance.
• Should be able to setup Digital design flows and methodologies including checklists, reviews to ensure quality designs and take them all the way to Silicon success.

【採用背景】
当社は「2035 Aspiration」の実現に向け、企業価値および時価総額の持続的な成長（約6倍規模）を目指しています。その実現を支えるため、IRおよびMarket Intelligence機能の強化が重要な経営課題となっています。

変化の激しい半導体業界およびグローバル資本市場の動向を的確に捉え、投資家・市場の視点を経営陣へフィードバックするとともに、企業価値向上に向けた戦略的な示唆を提供・推進できる人材を求め、本ポジションの採用を行っています。

【主な業務内容】

1. IR戦略の策定および実行
・投資家コミュニティにおける当社の認知度および評価向上を目的とした、包括的なインベスター・リレーションズ（IR）戦略を企画・立案し、その実行を主導する。
・経営陣と緊密に連携し、IR戦略および各種施策が当社の中長期的な経営戦略・事業戦略と整合するよう統括・推進する。
・財務情報、事業戦略、成長ストーリーを踏まえたIRメッセージングの全体設計を行い、開示および対話の一貫性を担保する。

2. マーケットインテリジェンスおよび経営へのフィードバック
・資本市場の動向、投資家の関心事項、評価軸、投資スタイルの変化を継続的に把握・分析する。
・競合他社のIR活動、開示内容、アナリストレポート、株価動向および株主構成の変化等を分析し、当社の市場でのポジショニングを整理する。
・投資家およびアナリストとの対話を通じて得られたインサイトを体系的に整理し、経営陣および関連部門へ適時にフィードバックする。
・これらの分析結果を踏まえ、株式価値向上およびIR戦略高度化に向けた示唆・提言を行う。

3. 投資家・アナリストとのコミュニケーションおよびリレーションシップ・マネジメント
・国内外の機関投資家およびセルサイド・バイサイドアナリストに対する主要な窓口として、戦略的かつ継続的なコミュニケーションを担う。
・当社の財務実績、経営戦略、成長戦略および中長期的な価値創造について、明確で一貫性があり、説得力のある説明を行う。
・投資家ミーティング、ロードショー、カンファレンス等の企画・運営および参加を通じて、当社のビジョンおよび業績を適切に発信する。
・プレスリリース、決算説明資料、プレゼンテーション資料、統合報告書・年次報告書等の投資家向け資料について、企画・作成・レビューおよび発信プロセスを統括する。
・FP&A／経理部門等の関係部署と連携し、正確性および適時性を担保した情報開示および対外説明を行う。

※就業場所の変更の範囲、従事すべき業務の変更の範囲については、選考時に詳細をお伝えいたします。

Job Summary

We are looking for an AI Application Engineer to support the enablement, optimization, and deployment of AI models on automotive-grade SoCs.

In this role, you will work closely with internal compiler/runtime teams and external customers to bring AI models from training to optimized inference on embedded NPU/DSP platforms, with a strong focus on performance, accuracy, and system integration.

Key Responsibilities

AI Model Enablement & Optimization

• Enable and deploy AI models (e.g., BEV, object detection, segmentation, classification) on Gen4/5 SoC platforms with CNNIP/DSP/NPU HWA.
• Perform model performance analysis (latency, throughput, multi-core scaling) and identify bottlenecks related to memory bandwidth, scheduling, or operator mapping.
• Support model optimization workflows, including:
  • Post-Training Quantization (PTQ)
  • Quantization-Aware Training (QAT) collaboration
  • Operator fusion, graph optimization, and execution partitioning
• Analyze accuracy degradation caused by quantization or operator limitations and propose mitigation strategies.

Embedded AI Inference & System Integration

• Integrate AI models into embedded runtime environments (Linux / QNX).
• Debug issues related to:
  • CNNIP/DSP/NPU offloading
  • Memory allocation / IPMMU
  • Data transfer overhead and multi-core synchronization
• Validate AI workloads on target boards and simulators (SIL / HIL).

Toolchain & Model Workflow Support

• Work with AI compiler and runtime toolchains (e.g., ONNX-based workflows, hybrid compiler, MWMX).
• Support ONNX model handling, including:
  • Graph inspection and modification
  • Model segmentation and execution control
  • Quantized (QDQ) ONNX models
• Develop or maintain internal tools and scripts to improve model validation, benchmarking, and customer workflows.

Customer & Cross-Team Collaboration

• Act as a technical interface between customers, internal development teams, and field application engineers.
• Support customer evaluations, PoCs, and demos on automotive AI platforms.
• Provide technical guidance, documentation, and best practices for AI model deployment.
• Contribute to weekly technical reports, issue tracking, and release validation activities.

【Background of the Recruitment】

As automotive electrification and intelligence continue to advance, automotive SoCs have become a core technology that directly supports vehicle performance and functionality.
The R-Car series has evolved as a large-scale automotive SoC through the advanced integration of a wide range of IPs, including CPU, high‑speed interfaces, memory, AI/video, functional safety, and security.
Among these technologies, high‑speed SerDes interfaces such as PCIe and CSI and DP and UCIe play a critical role in overall system performance and reliability.
As interface speeds continue to increase and system complexity grows, ensuring quality through thorough silicon‑level evaluation and signal integrity verification has become increasingly important.
In this context, we are seeking a technical leader who has hands‑on experience in high‑speed SerDes interface evaluation and can work closely with design teams and IP vendors to lead evaluation activities from a technical standpoint.
By taking ownership of evaluation and contributing technical judgment to development, this role is expected to play a key part in improving the overall quality of our automotive SoCs.

【Job Description】

• Lead the technical execution of high‑speed SerDes interface evaluation for automotive SoCs (R-Car series), covering interfaces such as PCIe, CSI, DP, UCIe, SerDes PHY, and other high‑speed I/F as applicable.
• Drive evaluation activities including silicon/board-level testing, signal integrity/quality assessment, stress testing, and standards/compliance confirmation, ensuring interface quality and robustness.
• Define and align evaluation strategy, organize test items, and consolidate evaluation results into actionable outputs for stakeholders.
• When issues occur, coordinate with design teams, SoC stakeholders, and IP vendors to perform triage, root-cause investigation, and countermeasure planning.
• Provide technical leadership to evaluation members across sites and functions, helping establish clear evaluation flow and decision criteria to improve overall execution quality

※The full details regarding your position scope as well as any future potential changes in work location and job scope will be provided during the interview process.

Renesas' automotive MCUs holds the No. 1 world-wide market share, and we are now aiming to expand our product lineup to achieve further business growth. Therefore, creating a need to strengthen the organization accordingly. Hardware Development is a vital element necessary to expand our business and this is also why we would like to invite talented Project Managers to join us on our mission.

Key Responsibilities

• Drive the Project development for automotive MCU products from Planning to MP (Mass Production) phase on schedule.
• Collaborate closely across multiple departments such as Customers, Software Teams, Marketing, Engineering, Finance, Sales and Vendors/Suppliers during project development phase.
• Deploy best Program Management Practices: Bottoms-up planning, Dependency mapping, Critical path analysis and Risk mitigation using industry standard planning tools such as MS-Project for Project planning and execution.
• Monitor the Project development progress and report the status on a regular basis and escalate issues whenever needed. Also provide regular Project updates to the Senior Management.
• Co-ordinate and Conduct Project Gate reviews.
• Take personal accountability to drive the projects and deliver them on schedule. Ensure proper project meeting cadence is in place and with regular follow-ups on ALL Action Items to resolve any open issues.
• Support Program Manager and project team in all organizational activities during the project development.

This role will be responsible for working closely with the Senior Director of Business Development (Corporate Strategy) and assisting in leading and overseeing strategic planning initiatives, with a focus on mergers and acquisitions (M&A) and other corporate transformation endeavours. The ideal candidate will have a strong background in M&A execution, strategic planning,  and corporate development. 

• Lead and manage M&A activities, including due diligence, negotiation and implementation of transactions and subsequent implementation activity.  
• Assist in the development and implementation of comprehensive strategic plans to drive growth and profitability. 
• Collaborate with cross-functional teams to ensure the effective delivery of a range of corporate strategy initiatives.  
• Provide strategic guidance and recommendations to senior leadership based on thorough analysis and evaluation  
• Conduct financial modeling and analysis to support strategic decision-making and investment prioritization. 
• Stay abreast of market dynamics, regulatory changes, and emerging technologies to inform strategic planning efforts. 
• Drive continuous improvement in strategic planning processes and methodologies. 
• Foster relationships with key stakeholders, including internal teams, external advisors, and potential partners 

• Partner with Business Leaders to develop and execute talent solutions for their business objectives and challenges
• Partner with HR CoE’s to support the design, roll out, and execution of programs.
• Champion initiatives that strengthen employee engagement, inclusion, and cultural alignment
• Manage country-level HR processes including performance management, compensation cycles, and employee relations
• Assist leaders in navigating organizational change, providing coaching and frameworks for effective decision making
• Leverage HR data analytics and dashboards to identify trends, measure impact, and influence leadership decisions
• Support local HR compliances.
• Partner with Business Leaders to develop and execute talent solutions for their business objectives and challenges
• Partner with HR CoE’s to support the design, roll out, and execution of programs.
• Champion initiatives that strengthen employee engagement, inclusion, and cultural alignment
• Manage country-level HR processes including performance management, compensation cycles, and employee relations
• Assist leaders in navigating organizational change, providing coaching and frameworks for effective decision making
• Leverage HR data analytics and dashboards to identify trends, measure impact, and influence leadership decisions
• Support local HR compliances.

Looking for a 5+ years experienced Engineer with good understanding of Analog concepts, experience of from scratch design of key analog blocks, integrating smaller blocks to create functional I/Ps and full ownership of those, ICs and well versed with Transistor level design flow, to join the 2.6B$ Power Business Unit. The candidate will get to work on a wide range of exciting products such as PMICs, Linear and Switching DC-DC converters powering the next generation of most sought-after phones and hand held devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.

Essential Functions:

• Must be proficient in designing and owning key analog blocks including Bangdap references, Analog Buffers, Op-Amps, Comparators, High speed level shifters etc.
• Must be able to come up with architectures to meet block level performance specifications.
• Must be well versed of the standard architectures and be able to bring in innovative ideas to improve designs to meet challenging specifications.
• Should have clear understanding of analog layouts and should be able to work closely with and guide layout engineers to ensure quality layout to meet the desired performance.
• Must be conversant with the standard design, extraction and simulation flows & tools, speed, convergence, accuracy trade-offs and should be able to optimize setups based on Pre/Post (with/without) Parasitic using simulator options, debug and navigate through tool related challenges.
• Should be able to mentor Freshers and Junior engineers for upscaling their technical skills as well as other skills needed for better efficacy.
• Should be able to develop multiple blocks with minimal supervision, take full ownership to drive all aspects within committed schedule and work closely with Sr members of Design team to support them build subsystem/chip top.
• Experience of silicon validation and debug is a strong advantage.
• Should have good understanding of ESD and be able to design the I/O ring for the IC

We are seeking a Senior Technical Recruiter with strong semiconductor industry expertise, particularly within Integrated Device Manufacturer (IDM) environments. The role leads the full end-to-end recruitment lifecycle while ensuring an exceptional experience for candidates and hiring managers, supported by high standards of data accuracy and process excellence. The ideal candidate is a hands-on technical recruiter with deep experience managing complex semiconductor requisitions and operating effectively in a fast-paced, global environment.

Key Responsibilities

End-to-End Technical Recruitment

• Lead the full recruitment cycle from requisition intake to offer acceptance.
• Develop tailored sourcing strategies for hard-to-fill semiconductor roles across design, manufacturing, test, packaging, and operations.

Sourcing & Screening

• Leverage multiple sourcing channels, semiconductor talent communities, niche platforms, referrals, and proactive market mapping.
• Build longlists and shortlists of qualified semiconductor professionals by applying role-specific technical filters across semiconductor HW & SW R&D IC design, fabrication, equipment engineering, process engineering, test development, and related fields.

Candidate & Stakeholder Management

• Provide high-quality CV presentations and candidate summaries to hiring managers.
• Advise hiring teams on market conditions, candidate availability, competitive intelligence, and recruitment timelines.
• Ensure consistent communication and outstanding experiences for candidates throughout the process.

Operation & System Excellence

• Manage all recruitment status updates in ATS, ensuring transparency and accuracy.
• Partner closely with cross-functional teams including HRBPs, HR Operations, and Business Leaders for compliance and smooth Process flows.

Industry Expertise

• Demonstrate strong familiarity with semiconductor roles across the IDM value chain, including:
  • R&D, IC design, physical design, verification
  • Process integration, yield engineering
  • Manufacturing, packaging, testing
• Maintain up-to-date knowledge of global semiconductor talent markets, competitive landscapes, and emerging skill trends.

• Lead cross-functional teams across Design, Systems, Validation, Product/Test Engineering, Firmware, Supply Chain, Procurement, and Quality to ensure seamless program execution in NPI projects.
• Lead COGS reduction programs from impact assessment through qualification, PCN, safelaunch, and production ramp – quantifying savings, evaluating ROI, and assessing the business impact of schedule slips and risk scenarios.
• Drive capacity expansion initiatives across global manufacturing sites, aligning engineering, operations, and supply chain to support production scalability.
• Build and manage detailed schedules for NPI, COGS and capacity programs; track progress, remove roadblocks, and implement data‑driven mitigation plans.
• Manage Engineering Build Request prioritization, conducting bi‑weekly reviews with PMO and Business Operations leadership to ensure alignment with organizational priorities.
• Act as a liaison between the product group, operations/supply chain teams, and key OSAT interface teams to ensure alignment, clarity, and seamless execution across all stages of the program.
• Drive sample readiness and ramp readiness, ensuring cross‑functional teams maintain schedules that support committed customer delivery timelines.
• Coordinate and conduct Project Gate reviews, ensuring cross‑functional readiness, milestone alignment, and clear communication of risks and dependencies.
• Oversee wafer fab, assembly, and test operations to ensure timeline adherence, cost efficiency, and quality standards across programs.
• Provide structured leadership updates on program status, risks, and mitigation plans, maintaining accurate schedules and qualification documentation.

【募集背景】

自動車の電動化・知能化により、車載SoCはクルマの価値を決定づける重要な技術領域となっています。
R-Carシリーズは、CPU、高速インタフェース、メモリ、AI／ビデオ、機能安全、セキュリティなど、多数のSoC IPを統合した大規模・高機能な車載SoCとして進化を続けてきました。
当部門では、自社IP開発に加え、他社IPの導入・組み込みを含むSoC IP開発を行っており、CPUサブシステムはその中核を担う重要な領域です。
開発規模・難易度の高いSoC開発を通じて、設計・検証・アーキテクチャ検討など、幅広い経験を積める環境があります。
本募集では、CPUサブシステム開発に携わり、専門性を活かしながら技術力を高め、将来のリーダー候補として成長していきたいエンジニアを歓迎します。

【業務内容】

• 車載SoC（R-Carシリーズ）における CPUサブシステム開発の実務を担当
• CPU、キャッシュ機構、メモリ周辺、バス／インターコネクト等を対象に、仕様検討、論理設計、検証、デバッグ、評価対応を通じて開発に関与
• 自社IPに加え、外部IP（CPUコア、キャッシュ、周辺IP等）の組み込み・調整・技術的な課題対応を担当
• 設計レビューや不具合解析の場に参加し、技術的な観点から意見出しや対応検討を行い、品質向上に貢献
• 日本・インド・ベトナムの設計拠点と連携し、グローバルな開発体制の中で役割を担う

※就業場所の変更の範囲、従事すべき業務の変更の範囲については、選考時に詳細をお伝えいたします。

Job Summary:
We are looking for a highly motivated and skilled engineer to join our Medium Voltage (MV) Power Trench MOSFET Design Team. The successful candidate will play a key role in the design and development of next-generation MV shielded-gate trench MOSFET technologies. This role involves close collaboration with process integration team, application team , marketing team and external foundry partners to drive innovation, optimize performance, and accelerate product industrialization.

Key Responsibilities:

• Define and establish key process modules for next-generation MV shielded-gate trench MOSFET technology
• Develop TCAD simulation decks and propose advanced device design concepts
• Analyze wafer-level electrical test results and package-level performance data for each development iteration
• Lead yield improvement activities and support technology transfer to mass production
• Contribute to the development of derivative products based on established and mature technology platforms

Role Summary
The Principal Engineer for Automotive Cybersecurity Governance & Compliance is responsible for leading the regional compliance strategy and technical governance for automotive MCU and SoC products across China and the APAC region. This role ensures that semiconductor platforms, reference architectures, safety manuals, and cybersecurity collateral enable OEMs and Tier 1 customers to achieve compliance with China GB 44495‑2024, GB 44496‑2024, CATARC‑directed certification activities, and UN R155‑based national implementations, including Korea’s Vehicle Cybersecurity Audit Framework.

The role acts as the technical authority and regulatory interface for cybersecurity certification impacts on MCU/SoC suppliers, bridging global product development teams, regional regulatory bodies, certification agencies, and customer compliance teams.

Key Responsibilities

1. China Automotive Cybersecurity Governance & Certification Leadership
2. UN R155 and APAC Regulatory Alignment
3. Korea Vehicle Cybersecurity Audit Framework Expertise
4. China Cryptography & PQC Strategy Awareness
5. MCU / SoC Cybersecurity Architecture & Evidence Enablement
6. Cross Functional & External Leadership

This position is expected to provide Test Operations and Engineering support for products post manufacturing release and deliver operational excellence through cost reductions, OEE, yield and cycle time improvements to achieve our test KPI goals with our Test Manufacturing Sites (Internal and Outsourcing Suppliers) in Malaysia, Thailand, Singapore and across Asia (Taiwan, China, Korea). This position reports into Operations Engineering Department (OED).

Key Responsibilities

• Responsible for Test Operations interface to Renesas Product Groups and other functional teams (Supply Chain, Quality, Packaging, Foundry, PMO) across US, Japan, India, Malaysia, and China on all phases of product lifecycle
• Execute daily test operations activities with internal factories and test OSATs to ensure customer delivery fulfillment (i.e. Lot tracking and dispositions, Test Program releases, Hardware Troubleshooting/Repairs, Equipment up-time, Tester Utilization OEE tracking, Continuous Improvement Process, etc)
• Coordinate Probe/Final Test transfer from New Product Introduction to High Volume Manufacturing from Renesas Product Group groups
• Execute new test capacity expansions (tester/ handler/ hardware) to ensure sufficient capacity and meet production demand
• Deployment of new tester/handler technology and test solutions to test manufacturing sites from test development
• Implement best known practices and process within test manufacturing sites
• Drive Gross Margins (OEE, Yield, Retest) improvement initiatives

We are actively driving advanced package technology and developing power package with focusing on next generation technologies for AI data center and automotive. To achieve the rapidly growing demand and expedite release to market of power packages, we are developing such as Power QFN, HSON, HSOT and TOLL. This role offers the opportunity to work on, higher density, lower resistance, higher reliability, and high thermal dissipation package design and develop technologies.

Key Responsibilities

• Design and develop power package and interconnect for Renesas’s packaging needs in the areas of power QFN, HSON, HSOT and TOLL for AI data center and Automotive.
• Work with OSAT/Internal manufacturing especially collaboration with Malaysia and Japan PKG team to develop, run DOE to optimize processes and establish process specification.
• Work with Product groups and QA team to define target of package structure/design, develop new package and processes, and qualify packages within required period.
• Ensure smooth transition into production by establishing robust design and process through the DOE results, verification, and resolving issuesduring development period.
• Develop and maintain technical expertise on advances and innovations in advanced power package design, process, and interconnect that linked and execute pkg roadmap.