Total 22 job vacancies by Advanced Micro Devices (singapore) Pte Ltd

THE ROLE:

Returns Debug and RMA execution in Quality & Reliability organization, provide supportive functions to the organization to ensure customer quality issue being addressed evoking the required actions via failure analysis to improve product quality.

THE PERSON:

You will also need to possess strong verbal and written communication skills which are essential when working with a global team. A proactive, outstanding teammate who focuses on teamwork, team building, and growing team success.

AMD's environment is fast paced, results oriented and built upon a legion of forward-thinking people with a passion for winning technology!

KEY RESPONSIBILITIES:

• Perform analysis & report writing on customer returns electrical FA, include analysis on Automated Test Equipment (ATE) and System Level Test (SLT), duplicate customer reported failure on Platform level and perform board level debug.
• Customer returns debug covering pre & post Mass Production, field return including Excursion/Critical issue, also cover debug for Defect Part Per Million (DPPM) improvement.
• Drive cross-functional collaboration by proactively engaging with Device Analysis and Product Engineering teams to lead fault isolation and root-cause investigations.
• Identify and define test coverage enhancements that strengthen product quality, prevent customer-facing failures, and support long-term reliability improvements.
• Provide technical direction in diagnosing complex issues, influencing validation strategies, and ensuring findings translate into actionable quality improvements across functions.
• Provide conclusive and convincing results and align with Program/PLQ/Customer Interfacing team on final analysis report writing for customer communication.
• Local product ownership roles that include but not limited to understanding, tracking and releases of ATE/SLT/OSV which covers RMA/OSV program, test program contents, and Go-To person on owned product technical queries.
• Role model as a coach for internal team that able to guide junior on technical challenges that arise during work for specific IP or failure category.
• Other duties as assigned by supervisor.

PREFERRED EXPERIENCE:

• Strong in silicon debug or Failure Analysis knowledge either on electronics system level or Integrated Chip.
• Candidate should be analytical and detail oriented, strongly interested in debugging complex system, self-starter, and fast learner
• Experience working in root causes digital or analog failure or SCAN/MBIST/High Speed Loopback failure.
• GPU, CPU or x86 architecture knowledge is much preferred
• Java, Python, Perl coding or Linux Shell scripting skills
• Window and Linux proficiency.
• JTAG knowledge is a plus.
• Knowledge in ATE test class/method experience with Advantest 93k platform is a plus.
• Experience in computing hardware, PC systems or Server platform projects or task is a plus.
• Knowledge or experience in PCB board or Customer Reference Board platform (schematics, layout, hardware configuration/setup, platform validation) is a plus
• Knowledge in industry standards like PCIE, USB, or high bandwidth memory is a strong plus
• Experience in AI or Machine Learning project or task is a plus. 

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in Electrical/Electronic Engineering or Computer Engineering

THE ROLE:

The candidate is responsible for driving advanced device development, reliability engineering, and process integration to enable robust technology development and qualification. This position plays a critical role in supporting next-generation technology exploration through close collaboration with DTCO, design, and technology teams across global sites.

THE PERSON:

This role requires a candidate with a proactive mindset and the ability to work independently, while also demonstrating strong collaboration skills within a team-oriented environment.

KEY RESPONSIBILITIES:

• Drive advanced device development and process integration activities, leveraging deep understanding of semiconductor device physics and process optimization.
• Support technology development, qualification, and ramp, ensuring robust device performance and manufacturability.
• Lead or support reliability engineering efforts, including identification and analysis of key failure mechanisms.
• Develop and maintain design guidelines for TDDB, aging, and electromigration, translating foundry reliability rules into actionable design practices.
• Collaborate closely with DTCO, design, and technology teams to optimize design–process interactions.

PREFERRED EXPERIENCE:

• 10+ years of hands-on experience in semiconductor technology development, with strong background in: Device physics, Process optimization, Reliability engineering
• Proven experience in advanced CMOS technologies (e.g., FinFET, GAA, or equivalent advanced nodes).
• Solid understanding of device reliability fundamentals and process–device interactions.
• Demonstrated understanding and hands-on experience with SPICE simulation and related scripting or programming languages.

ACADEMIC CREDENTIALS:

• Educational Qualification: Master's degree required; Doctoral degree preferred.

• Field of Study: Degree in Electrical Engineering, Materials Science and Engineering, or a related field.
  

THE ROLE: 

As a Senior Engineer, you will collaborate with various Product Development Groups. This individual serves as a critical technical point of contact to the business, design, platform validation and product engineering teams. We have competitive benefit packages and an award-winning culture. Join us!  

THE PERSON: 

A successful candidate is one who can drive technical decisions independently, has accountability for accuracy, reliability and completeness of assignment results critical to the project’s success. This role allows the opportunity to influence technical decisions that have a significant impact on multiple products or the product line.  

KEY RESPONSIBILITIES: 

• Ensures high uptime, ensures preventive maintenance (PM) execution, and seamless vendor coordination for resolving tools hardware and software issues. Primary advanced toolset coverage: Focused Ion Beam, Reactive Ion etchers, Nano‑probers, Scanning electron microscopes and Transmission electron microscopes 
• The role partners closely with equipment owners, lab operations, EHS, and external OEMs to sustain capability, drive MTBF/MTTR improvements, and enable rapid turns on high‑priority cases.
• Design new lab space with strict environmental control involving vibration, EMI and acoustics.
• Lead structured troubleshooting and root‑cause eradication (5‑Why, Ishikawa, FMEA); convert escapes into standard work and documented fixes
• Serve as single point of contact for OEMs and third‑party service providers; coordinate field service, escalations, and remote diagnostics
• Manage service contracts, PM bundles, and time‑and‑materials events; negotiate scope vs. cost; track vendor KPI adherence and corrective actions
• Enforce LOTO, ESD, chemical/gas handling, UHV safety, and radiation/beam compliance as applicable
• Partner with FA engineers on readiness gates for new methods/fixtures; support tool installation, lab moves, and capability upgrades
• Provide on‑call/shift coverage as needed for bring‑up, critical debug, and factory‑stop events

PREFERRED EXPERIENCE: 

• Hands on maintenance experience with complex capital equipment involving vacuum systems, motion/servo control, pneumatics, high voltage, and embedded SW/FW
• Demonstrated ability in systematic troubleshooting, reading electrical/pneumatic schematics, and using diagnostic tools (oscilloscope, DMM, leak detector, RGA)
• Effective communication with vendors and cross site teams; ability to coordinate multi party interventions under time pressure
• Experience in failure analysis tools, including alignments, stage/probe calibration, column health, and detector
• Knowledge of UHV, turbo/cryogenic pumps, gas handling, plasma sources, beam columns, and vibration/thermal isolation
• Lab‑based role with occasional off‑shift or weekend coverage during critical events and planned PMs
• Some travel for OEM training, factory repair, or acceptance tests may be required

ACADEMIC CREDENTIALS: 

• Bachelor’s degree in Mechatronics Engineering (or Mechanical/Electrical with mechatronics focus)

THE ROLE:

As a New Product Introduction Product Engineering Manager, you will lead the Product Engineering (PE) team under the Product Engineering Organization (PEO) to develop exciting next generation AMD products. You will work closely with world class Product Test, Design, Quality, Reliability, Customer, Software and Platform global teams to plan and develop the final product solution to meet Cost, Yield and Quality targets. With close collaboration with end customers, you will also have insights into the product and guide your team to achieve customer expectations.

THE PERSON:

We are looking for someone with strong technical, analytical, leadership and problem-solving skills, as well as demonstrating the characteristics of an independent and resourceful individual. Preferably, the candidate should have experience in leading NPI teams and understanding the ecosystem of product development. Good communication is also key to successful collaboration. 

KEY RESPONSIBILITIES:

• Lead the Product Engineering team in silicon characterization and analysis to develop Product Definition to meet customer requirements and achieve Yield and Cost target.
• Interface with US product groups, design, platform validation, BIOS and test engineers on root cause resolution for device failures along with power and performance settings.
• Provide Product Technical leadership to PEO teams, drive alignment among teams to achieve product technical requirements.
• Oversee device and process reliability, assess implications of stress-testing outcomes, balance business and quality/reliability requirements for Products and Processes in question
• Set goal, plan and coordinate (data analysis, debug, root-cause, implementing solutions) yield improvement activities.
• Lead effort to optimize product positioning to meet business requirements, from Fab Assembly
• Provide timely debug for customer reported issues, assist customer and quality teams to provide resolutions.

PREFERRED EXPERIENCE:

• Analytical Thinker: able to assess problems, plan for experiments/next steps and drive team to execute.
• Data Analytics: able to understand complex data and draw technical conclusions to drive the next step.
• Experience in Product Management methodology, fab process and/or x86/GPU/High Speed IO operation is preferred.
• Perform new device characterization, circuit sensitivity analysis, interpret findings and work with the technical teams to root-cause, and/or provide mitigation actions for any observations.
• Work with global teams across the organization during New Product Introduction phase to validate new device features and test/DFT methodologies, and implement them in production flow while balancing yield and quality
• Strong and effective presentation, written and verbal communication skills, and the ability to work with geographically distributed product engineering teams.
• Excellent interpersonal and organizational skills.
• Experience in leading small teams.
• 10yrs or more experience in the semiconductor industry and worked on NPI 

ACADEMIC CREDENTIALS:

• BS/MS Electrical Engineering, Computer Engineering, or comparable disciplines

THE ROLE: 

This position is responsible managing the end-to-end supply planning for Data Center GPU products to support the growth in our Data Center GPU business. They will be accountable to meet key performance indices and drive system and process improvements. The ideal candidate will have a healthy intolerance for the status quo, intellectual curiosity, comfort with uncertainty, and a process mindset. This role demands customer focus, strong decision-making capabilities, agility, and excellent communication skills to effectively manage supply across multiple functions & geographies.

KEY RESPONSIBILITIES:

• Accountable to meet KPI for SCM: meet program milestone, on-time-delivery, revenue attainment
• Collaborate with other functions to communicate priorities, strategies, and close operational gaps
• Performs analysis to proactively identify potential shortages and drives expedites to close the gap
• Manage and position supply to meet new product milestones & demand ramp and manage risk
• Responsible for continuous supply and demand tracking and analysis and action as needed
• Manages and converts demand to a master schedule to meet customer deliveries
• Collaborate with stakeholders to resolve issues or identify innovative solutions
• Lead resolution of issues to meet customer success or enable decision
• Drive robust tool development to manage complex planning, BOM, and inventory flows
• Advocate and drive continuous improvement & change management process design to increase productivity and scale
• Proactively analyze to identify and minimize excess supply during the NPI product phase
• Able to work with all levels and functions of the organization
• Facilitate or represents NPI Operations in group discussions or meetings

PREFERRED EXPERIENCES:

• Relevant work experience in Industrial Engineering, Supply Chain or Operations Research
• Growth mindset, team player, collaborative, solid deductive reasoning
• Must have strong analytical and quantitative skills, proficient at Microsoft Excel and PowerPoint
• Effective verbal and written communication skills
• Pro-active, resourceful, able to multitask in dynamic conditions and handle pressure
• Solid understanding of the semiconductor supply chain and manufacturing flow desired
• Able to work well with cross functional teams and in a matrix organization
• Strong experience with SAP, Rapid Response a plus.

THE ROLE:

We are the high-end test engineering team providing test solutions for Data Center Graphics (DCG) New Product Introduction (NPI) under the Product Engineering Organization. We do exciting product development for leading-edge technology that will power the next generation processors used for high performance computing, data centers, enterprise servers, and Artificial Intelligence clusters.

If you are looking for a fulfilling and challenging career as a Manager/ Lead in NPI System Level Test (SLT) Product Development, you are at the right place! As a SLT Product Development manager you will be responsible for leading and driving SLT solution to meet NPI business milestones and KPI (test time, yield, cost, quality). The expectation is to perform leadership through interaction with design teams, Product & Test Engineering teams, Customer Quality teams, software & platform teams to come up with the best solution that balance quality and cost. You will experience working with and learning from AMD’s talented engineering teams around the world.

THE PERSON:

We are looking for someone with strong technical, analytical, leadership and problem-solving skills, as well as demonstrating the characteristic of an independent and resourceful individual.

The applicant must have a proficient understanding of x86 CPU and GPU architecture and functionality, as well as a broad understanding of various industry standard bus protocols, such as DDR, PCIe, and USB. 

KEY RESPONSIBILITIES:

• Lead the development of SLT Test Program infrastructure to meet business milestone, cost and quality in system level area.
• Solves complex, novel, and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation
• Conduct engineering evaluations and analysis to drive closure of production issues
• Lead the development and architect of SLT logging or data collection flow in manufacturing
• Influences technical decisions that have a significant impact on final product
• Involves collaboration on or assuming the consultative or leadership responsibilities for a specific project or for product development initiatives
• Provides technical supervision or mentoring of engineers
• Upscale overall team capabilities on system debug for AMD data center product families
  
  

PREFERRED EXPERIENCE:

• Knowledge or working experience on GPU architecture, X86 architecture, SoC design and power management features
• Experience with SOC (System-On-Chip), Firmware and Software interaction
• Software programming and scripting proficiency (Java, Shell script, Perl, Ruby, Python)
• Proficiency in Windows, and Linux operating systems
• Experience with HBM (High Bandwidth Memory) or HSIO (High Speed Input Output) is a strong plus
• Experience with HVM (High Volume Manufacturing) is a strong plus
• Experience with data center infrastructure is a strong plus
• Strong and effective presentation, written and verbal communication skills, and the ability to work with geographically distributed engineering teams
• Excellent interpersonal, organizational, and analytical skills
• Experience in leading mid-sized teams.
• Ability to manage multiple projects and meet tight deadlines.
• >7-10 years or more industry experience

ACADEMIC CREDENTIALS:

• BS/MS Electrical Engineering, Computer Engineering, or comparable disciplines

THE ROLE:

We are a growing Product and Test Engineering team who manages critical and strategic New Product Introduction (NPI) and sustaining to support the Embedded Business Unit. We do exciting product development based on leading-edge technology that will power the next generation processors used for automotive, robotics, high-end networking and storage, industrial, aerospace and defense.

 If you are looking for a fulfilling and challenging career as an engineer in NPI System-level Test (SLT) Product Development, you are in the right place! As a Member of Technical Staff (MTS) SLT Product Development Engineer, you will be responsible for developing and driving SLT test solutions to meet production business milestones and KPI metrics (test time, yield, cost, quality). The expectation is to perform technical leadership through interaction with Diagnostics team, Quality & Reliability team, BIOS, software & platform teams to come up with the best solution that balances quality and cost. You will experience working with and learning from AMD’s talented engineering teams around the world.

THE PERSON:

As part of this team, you will have complete ownership in developing SLT test program for next-generation AMD microprocessors. You will work on internal SLT platforms and debug test infrastructure issues including test HW, test SW, diagnostics, and device-specific IP.  Additionally, you will leverage SLT data to drive improvements in either the product’s platform software or upstream ATE test coverage.  The engineer must ensure overall compatibility, compliance, and test coverage of microprocessors from product definition through product qualification and into high-volume manufacturing by developing product specific test hardware, software, and diagnostics.

KEY RESPONSIBILITIES:

• Accountable for driving test solution/coverage development, optimization to meet business milestones: schedule, test time, yield, cost and quality.
• Must have a strong proven track record of NPI experience in directing SLT Test patterns, calibration test flows/method development, debug, test and characterization experience working in an NPI Product Engineering team.
• Collaborate with various engineering teams to determine System Level Test (SLT) coverage, content, characterization requirements, and root cause resolution for SLT device failures
• Early engagement in pre and post silicon phases, including test flow planning, test coverage bring-up, test flow integration, and test hardware checkout.
• Validate new product features, test conditions, test methodologies, and test contents
• Perform silicon characterization across process, voltage, and temperature
• Conducts engineering evaluation, test program correlation, releases for high volume production and engineering enhancement or improvement projects
• Drive Key Performance Indicators such as test time reduction, yield debug, quality improvement across products and drive innovation on test strategy
• Provides overall Test Engineering support for AMD’s S3 products tested at global facilities
• Working with regional teams, including Product development group and Manufacturing group in the early stage bring up for product cycles at the AMD high volume sites
• Represents test team on any test excursions and issue escalations to the respective owner to identify resolution or containment action for the issue
• Interface between AMD and OSAT for test program implementation and resolution for operation issues
• Requires strong understanding of test program, good communication and capability to drive/deliver critical business milestones
• Provide technical supervision or mentoring junior engineers
• Familiar with RMA debug is a plus.
  

PREFERRED EXPERIENCE:

• Mastery of principles of test experience in System Level Test or x86 System Architecture
• >10 years of SLT technical leader with a successful track record of bringing up test patterns, debug low yield, test flow integration and characterization experience working in an NPI Product Engineering team.
• Proficient in Windows, Unix, and Linux operating systems
• Experience in platform test and debug
• Experience with IC test experience and assist in ASIC bring up and support activities
• Technical knowledge in OS kernel, driver, BIOS firmware
• Demonstrated programming and scripting experience using various programming languages (C, C++, Java, Ruby, Perl, Python)
• Knowledgeable in version control tools (Git)
• Electrical/Electronics, Computer Engineering, or comparable disciplines

ACADEMIC CREDENTIALS:

BS/MS Electrical Engineering, Computer Engineering, or comparable disciplines

THE ROLE:

Test Engineering is a cost, quality, and time-to-market driven team responsible for enabling the availability of FPGAs, SoCs & ACAPs to our customers.  The Test Engineer will be involved in new product release as well as production yield/quality improvement activities.  This role requires close collaboration with Test Pattern Developers & Product Engineers to create test programs that provide optimum test coverage for our products.  There are also ample opportunities to work on cost reduction and test capacity improvement projects.    

THE PERSON:

Looks forward to new challenges. Has good analytical and problem-solving skills. Enjoy working in cross-functional teams. Has effective communication and presentation skills.

Fluent in both oral and written English.

KEY RESPONSIBILITIES:

• Develops ATE test programs to test FPGA & SoCs products.  This involves constructing or enhancing test methods, and integration of timings/ levels and test flow into a test program.
• Involved with New Product Introduction process and works with test pattern developers in generating, debugging, and implementing new test patterns.
• Other duties include working with product/yield engineers in implementing new test requirements for yield and quality improvements; as well as working on productivity improvement and cost reduction activities such as test time reduction and multi-site development & implementation.
• Implement and manage efuse operations: ability to read fuse maps, develop and maintain secure burning procedures, read-back verification, trim and CRC flows.
• Understanding basic symmetric and asymmetric cryptographic functions (e.g., AES, SHA, RSA/ECC).
• Analyze large test datasets to drive yield improvement, failure analysis, and continuous optimization; build automated dashboards and reports.
  
  

PREFERRED EXPERIENCE:

• The candidate should have 5 or more years of ATE test program development experience. In-depth knowledge and hands-on experience in one or more of the following ATE platforms are desired: Advantest T2000 and/or Verigy93000 (Smartest 7/8).
• There should be a proven track record of developing and releasing new test programs to production.  Good understanding of test concepts & new product development cycle is desired.
• Advanced proficiency in Python and C++ for ATE test development, tooling, and data analysis; experienced with libraries such as OpenSSL, NumPy, and Pandas, and capable of designing and maintaining robust regression test suites.
• Practical experience with Git for version control and Confluence for documentation and knowledge management.
• Strong hands-on Linux skills for development, automation, scripting, and environment management.

ACADEMIC CREDENTIALS:

• Bachelor’s or master’s degree in Electronics Engineering
• Specialization in Electronics or Computer Engineering is preferred.

THE ROLE:

We are the high-end test engineering team providing test solutions for Data Center New Product Introduction (NPI) under the Product Engineering Organization. We do exciting product development for leading-edge technology that will power the next generation processors used for high performance computing, data centers, and enterprise servers.

If you are looking for a fulfilling and challenging career as an engineer leading SLT (System Level Test) Thermal and Board SME (Subject Matter Expert), you are at the right place! As a MTS System Level Technical Lead, you will be responsible for defining, driving and enabling SLT test solution to meet NPI business milestones and KPI (test time, yield, cost, quality .The expectation is to perform leadership to have interaction with Silicon/Board/Power design teams, Product & Test Engineering teams, Customer Quality teams, software & platform teams to ramp GPU coverage with aggressive schedule while debug GPU fallout to ensure high yield. You will experience working with and learning from AMD’s talented engineering teams around the world.

THE PERSON:

We are looking for someone with strong technical, analytical, leadership and problem-solving skills, as well as demonstrating the characteristic of an independent and resourceful individual.

You will be proficient in your understanding about PCB Board and High Power Delivery (above 1kW) design methodology, Thermal dissipation as well as a broad understanding of various industry standards in OCP (Open Compute Project), such as JEDEC HBM3/4, PCIe, I2C/I3C, UEC (Ultra Ethernet Consortium) and UCIe (Unified Chiplet Interconnect Express) etc.

KEY RESPONSIBILITIES:

• Accountable to provide leadership to meet business milestone, cost and quality in GPU system level test area.
• Collaborate with internal teams to drive SLT board and power swim lane from pre-silicon, ASIC initial bring up to HVM (High Volume Manufacturing)
• Conduct engineering evaluations and analysis to drive closure of GPU production issues, qualify cutting-edge high power SLT thermal system for HVM
• Profile or characterize PI (Power Integrity), voltage droop, or power delivery issue observed on SLT platforms in collaboration with board/silicon designers
• Involves collaboration on or assuming the consultative or leadership responsibilities for a specific project or for product development initiatives
• May provide technical supervision or mentoring junior engineers
• Upscale overall team capabilities on low level system debug for AMD data center product families

PREFERRED EXPERIENCE:

• Experience and with good understanding of PCB board and Power Delivery design for high power GPU product (above 1kW), and board lifecycle from Eval to HVM (High Volume Manufacturing)
• Strong expertise with using analyzers and oscilloscopes, and other debug tools
• Knowledge and working experience on GPU and HBM architecture, SoC design and SoC power management features are a strong plus
• Strong and effective presentation, written and verbal communication skills, and the ability to work with geographically distributed product engineering teams
• Proficiency in Windows, and Linux operating systems
• Basic scripting proficiency for automation (Shell script, Perl, Ruby, Python)

ACADEMIC CREDENTIALS:

• BS/MS Electrical Engineering, Computer Engineering, or comparable disciplines

THE ROLE:

You will be as part of the Product Engineering Organization, where we deliver test and manufacturing solutions for Enterprise New Product Introduction (NPI). You will be at the forefront of developing innovative products that drive next-generation processors for high-performance computing, data centers, and enterprise servers. As a Staff Automatic Test Equipment (ATE) Test Engineer, you will collaborate with design teams to guarantee the timely delivery of high-quality ATE Test solutions. You will assume ownership of specific test modules and/or the overall Test program, which involves ensuring content development and bring-up is in accordance with established validation protocols. You will be developing ATE test programs and designing test hardware for supported products. Additionally, you will evaluate and release robust test programs for production testing, ensuring that all quality, yield, and test time performance indicators are consistently met.

THE PERSON:

You will have a deep commitment to technical expertise, who is eager to continuously learn and share knowledge within the team. You should possess a robust background in ATE development, preferably Advantest 93K, focused on test content and program creation. You will be results-driven and demonstrate strong stakeholder management skills, essential for effective collaboration with diverse teams across AMD. Excellent verbal and written communication abilities are required for successful engagement with our global workforce.

KEY RESPONSIBILITIES:

• Partner with IP design, validation, and architecture teams to ensure comprehensive IP content coverage, and to develop, validate, and debug test patterns.
• Build and maintain test program infrastructure, leveraging the latest Best Known Methods.
• Evaluate and validate new product features, test conditions, methodologies, and test content during initial silicon bring-up.
• Conduct silicon characterization across various process, voltage, and temperature conditions.
• Correlate and release test programs for high-volume production environments.
• Lead initiatives to improve Key Performance Indicators, focusing on reducing test time, debugging yield issues, and enhancing product quality.
• Provide support for product qualification processes and assist in debugging customer returns.

PREFERRED EXPERIENCE:

• Hands-on experience developing ATE test programs and patterns, with a preference for Advantest 93K platforms.
• Understanding of JTAG, BIST, and HSIO concepts.
• Experience designing ATE loadboards.
• Strong programming and scripting skills in languages such as C, C++, Java, Ruby, Perl, or Python.
• Familiarity with version control systems
• Competence in statistical analysis techniques.
• Proficiency in Windows, Unix, and Linux operating systems.
• Solid understanding of modern computer architecture.

ACADEMIC CREDENTIALS:

• BS/MS Electrical Engineering, Computer Engineering, or comparable disciplines

LOCATION:

Singapore

THE ROLE:

We are looking for an experienced Verification Engineer to join our team for cutting-edge server memory products. This individual will be responsible for driving the verification efforts of DDR interfaces, including advanced memory protocols such as DFI, DDR5, and LPDDR5/LPDDR6, across a range of DIMMs (Dual In-line Memory Modules). The ideal candidate will possess advanced knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python/Perl.

THE PERSON:

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc.  You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:

• Work with a team verification engineers in the development and execution of verification plan for DDR5, LPDDR5, and DFI memory systems in server products.
• Comprehend the PHY's interaction in the complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features of the memory interface.
• Understand RTL and micro-architecture sufficiently to engage in cross functional discussions with IP/Domain architects and Design engineers for planning and debug.
• Knowledge sharing and other contributions to verification methodology
• Support Post-Si teams for Product Performance, Power and functional issues debug/resolution 

PREFERRED EXPERIENCE:

• Developed and implemented SystemVerilog and UVM (Universal Verification Methodology) based testbenches, simulation environments, and functional coverage models for DDR5 and LPDDR5 systems.
• Worked closely with hardware, firmware, and software teams to align on system-level memory architecture, identify potential integration issues, and define validation requirements early in the design phase.
• Built VIPs and BFMs for memory interfaces from scratch (preferrable)
• GLS, NLP, XPROP simulation experience is preferable
• Strong proficiency in system verilog assertions, constraints and coverage.
• Worked in formal verification methods, with proven record of tool usage beyond the standard apps.
• Excellent communication, management, and presentation skills. 

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in related discipline

THE ROLE:

We are seeking a Staff Packaging Engineer to lead advanced package industrialization from NPI through HVM, driving DFM integration and manufacturing readiness with OSAT partners in multiple countries to ensure stable ramp, yield, quality, and delivery performance.

THE PERSON:

Based in Singapore, you will work closely with OSAT operations and engineering teams across multiple countries, partnering daily with manufacturing engineering, quality, and operations to establish/maintain POR, close manufacturing gaps, and rapidly resolve factory issues across advanced packaging technologies (e.g., 2.5D interposer and fan-out).

Collaborate cross-functionally (design, substrate, reliability, test, quality, supply chain, and program management) and apply structured methodologies (DFM/DOE/SPC/FMEA/8D) to drive risk reduction and ramp readiness.

This is an execution-driven role requiring strong advanced packaging process expertise, manufacturing / operations acumen, and the ability to influence across global teams and external partners to deliver robust, scalable production.

KEY RESPONSIBILITIES:

NPI to HVM Industrialization

• Lead end-to-end industrialization of advanced package technologies from NPI through HVM readiness across external assembly/test manufacturing partners and foundry partners.
• Own NPI-to-HVM execution: lead readiness reviews, drive risk mitigation, and govern ramp activities; collaborate closely with OSAT engineering teams on process development, qualification, and optimization to ensure robust, scalable, and manufacturable assembly and test solutions across sites.

Design for Manufacturing (DFM) Integration

• Primary interface between package design/technology development and external manufacturing partners to ensure manufacturable architecture and clear DFM requirements.
• Identify/close manufacturability gaps early; drive technology-to-manufacturing transfer and best-practice deployment.

External Supplier Manufacturing Management

• Partner with outsourced manufacturing sites to ensure manufacturing capability, capacity readiness, and process maturity for advanced packaging platforms.
• Drive yield, cycle time, quality, and delivery performance; lead defect reduction and yield improvement with site teams.
• Provide hands-on execution leadership OSATs: lead daily/weekly manufacturing reviews, expedite issue triage with site teams, and align action owners across manufacturing, quality, and supply chain to protect ramp and delivery.
• Manage out-of-control lot disposition; implement CAPA and share BKM.
• Lead technical reviews, audits, ramp readiness assessments, and coordinated change management with internal/external stakeholders.

Yield, Quality, and Process Control

• Drive process control and continuous improvement using DOE/SPC/FMEA and data-driven root cause analysis.
• Lead cross-functional investigations for yield excursions, reliability risks, and field quality issues, ensuring timely containment and corrective actions (8D).
• Develop monitoring/early-detection mechanisms and ensure alignment to quality, reliability, and qualification requirements.

Cross-Functional Program Execution

• Partner cross-functionally (design, tech dev, reliability, product/test, quality, supply chain, program management) to align deliverables and execute to plan.
• Drive readiness reviews and risk assessments; track actions and communicate clear status/escalations to stakeholders.
• Support program teams in achieving cost, schedule, capacity, and production targets for Enterprise, Client, and AI accelerator products.

PREFERRED EXPERIENCE:

• Experience in semiconductor packaging/assembly manufacturing or product engineering, with strong on-site execution in high-volume environments.
• Proven NPI and ramp leadership, including supplier management, process qualification, manufacturing readiness, and yield ramp monitoring.
• Demonstrated ability to work effectively with OSAT manufacturing operations in multiple countries, including structured communication, escalation management, and fast-turn coordination across site teams and global stakeholders.
• Demonstrated success in yield improvement/defect reduction, root-cause closure, and disciplined change management in HVM.
• Hands-on advanced packaging experience (e.g., 2.5D interposer, fan-out, 3D, high-density flip-chip; plus RDL/TCB/hybrid bonding familiarity) with OSAT/factory interface experience.
• Strong problem-solving and analytics using structured methods (DOE/SPC/FMEA/8D) and manufacturing data to drive decisions.
• Strong stakeholder management across cross-functional teams and external partners; able to translate issues into clear action plans and drive closure.
• Professional fluency in English, Mandarin, and Korean to support technical documentation, stakeholder communication, and cross‑site engineering collaboration across APAC.

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in Mechanical Engineering, Materials Science, Electrical Engineering, Chemical Engineering, or a related engineering discipline.

THE ROLE: 

We are looking for an adaptive, self-motivative Design Verification (DV) engineer to join our growing PLL team. As a key contributor, you will be part of a leading team that drives and improves AMD's ability to deliver the highest quality, industry-leading technologies to the market. The Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. 

THE PERSON:

• Excellent analytical and critical thinking skills along with attention to details
• Must be an initiative-taker, able to drive tasks independently and efficiently to completion
• Strong/effective communication skills
• Enthusiastic team-first mentality
• Ability to provide mentorship and guidance to junior engineers

KEY RESPONSIBILITIES:

• Analyze complex verification and digital design problems and propose verification / micro-architecture solutions

• Develop RTL and Firmware validation.

• Drive/develop ASIC verification flows and scripts.

• Create Verification architecture.

• Work with the RTL Design team to ensure functional correctness and coverage.
• Support silicon bring-up and diagnostics.

• Support Post-silicon debug, root cause bug, provide solution or workaround.

PREFERRED EXPERIENCE:

• Proven experience in design verification from specification to successful silicon.
• Experience in PLL, high-speed interfaces such as DDR, PCIe and high-speed SERDES.
• Experience in designs with multiple power domains.
• Experience in designs with multiple clock domains.
• Experience in behavior modeling for Analog Circuits.
• Experience in industry-standard ASIC CAD tools for verification, simulation, synthesis, STA, CDC, UPF, power estimation, etc
• Progressive experience in RTL Design

ACADEMIC CREDENTIALS:

• Bachelors or Masters Degree in Computer Engineering/Electrical Engineering 

THE ROLE:

This role is responsible for end‑to‑end ATE test solution architecture and execution for next‑generation AMD products. This role owns technical leadership across pre‑silicon planning and post‑silicon execution, ensuring that ATE test solutions meet AMD’s quality, performance, cost, and reliability objectives while enabling fast time‑to‑market.

This position partners closely with Design, Product Engineering, Platform Engineering, Device Analysis, Foundry, Quality & Reliability, Manufacturing, and OSAT teams to define and deliver robust, scalable ATE strategies across wafer sort and final test. The role acts as a technical authority and lead engineer, guiding teams through complex test challenges and driving innovation in test methodologies and manufacturing processes.

THE PERSON:

This is a senior individual contributor leadership role for a highly experienced test engineer with deep hands‑on ATE expertise and strong technical influence. The ideal candidate brings a proven track record of owning ATE test solutions across multiple product cycles, making critical technical decisions, and influencing cross‑functional stakeholders without formal people‑management responsibility.

The candidate is expected to operate as a subject‑matter expert and technical leader, setting direction, mentoring senior engineers, and shaping best practices across ATE domains. This role requires a strategic mindset, strong execution discipline, and the ability to balance test coverage, yield, cost, and schedule trade‑offs in high‑stakes product environments.

KEY RESPONSIBILITIES:

Technical Leadership & Ownership

• Own pre‑silicon ATE planning and post‑silicon execution for assigned product groups, from early architecture through HVM ramp.
• Define and drive ATE test strategies and architectures aligned with product roadmaps and business priorities.
• Serve as the technical authority for ATE readiness at all NPI milestones, including first silicon, bring‑up, characterization, qualification, and high‑volume manufacturing.
• Lead design collaboration to achieve First Time Right (FTR) ATE test patterns in a disciplined, time‑bound manner.

Product Engineering & Execution

• Define and execute product engineering test strategies that enable robust validation, characterization, and manufacturability.
• Drive yield improvement, test time reduction, and cost optimization through test program architecture, pattern optimization, and data‑driven analysis.
• Support multiple product families concurrently by promoting reuse, common platforms, and scalable methodologies.
• Troubleshoot and resolve complex test, silicon, and manufacturing issues across wafer sort and final test.

Cross‑Functional Collaboration

• Partner closely with Design, Verification, Test, Product Engineering, Software, Manufacturing, and Operations teams to ensure test solutions meet quality, reliability, and cost targets.
• Work directly with OSAT partners and internal factories to ensure consistent, high‑quality production execution.
• Act as a key technical interface across global teams, influencing decisions through data, expertise, and credibility.

Innovation, Data & Advanced Methodologies

• Drive the adoption of advanced data analytics, AI, and ML techniques to improve test efficiency, yield learning, and decision‑making.
• Champion continuous improvement through new processes, tools, automation, and state‑of‑the‑art ATE methodologies.
• Establish best practices and technical guidelines that improve productivity and scalability across ATE teams.

Mentorship & Technical Influence

• Mentor senior and staff‑level engineers, providing technical guidance and design reviews.
• Contribute to capability development, technical roadmaps, and succession planning in partnership with management.
• Influence technical direction across teams without direct people management responsibility.

Quality & Compliance

• Ensure compliance with internal processes, manufacturing standards, and ISO requirements.
• Maintain high quality of deliverables and disciplined execution across all phases of product development.

PREFERRED EXPERIENCE:

• Experience in the semiconductor industry with deep specialization in ATE test engineering
• Strong hands‑on expertise in: ATE test methodologies, DFT and testability concepts, Product characterization, qualification, and manufacturing test
• Proven track record of owning ATE test solutions across multiple full product cycles (pre‑silicon to HVM)
• Experience working with outsourced test (OSAT) models and high‑volume manufacturing environments
• Strong background and demonstrated results using data analytics, AI, or ML in test or manufacturing contexts
• Ability to drive complex technical decisions across cross‑functional teams
• Exceptional analytical, problem‑solving, and troubleshooting skills
• Strong communication and influencing skills in multi‑site, multicultural environments
• Demonstrated openness to innovation and continuous improvement

ACADEMIC CREDENTIALS:

• Bachelor/Master in Electrical/Electronic Engineering

THE ROLE:

The Technical Lead is responsible for the test solution for a next-generation AMD Products. This position serves as the Test Engineering team's Technical Leader and go-to expert for solutions.  This position requires engagement with Product, Design, Platform Engineering, Device Analysis, Foundry, Quality and Reliability Engineering to drive test and characterization plan, 1st silicon bring-up, silicon debug, attainment and optimization of yield and performance distributions, test costs and product quality for next-generation AMD products.

This role offers opportunities for experienced Engineers who are interested in growing their technical scope over time, based on individual performance and business needs.

THE PERSON:

We are looking for one with a passion for technical development, possessing broad technical leadership, critical problem solving and troubleshooting skills. The person must be a team player and have good and effective communications to deep dive into technical discussion with other members across the globe and use data to illustrate their points. This person is expected to be independent, self-starter, well organized and have the sense of responsibility to see projects through beginning to the end as well as the ability to lead by influence. This person is expected to be market savvy and comfortable in a multi-tasking environment.

KEY RESPONSIBILITIES:

New Product Introduction (NPI)

• Define and drive pre silicon test and characterization strategies for complex SoC products.
• Establish DFT and pattern requirements, and work with Design and Verification teams to ensure test readiness prior to first silicon.
• Lead first silicon bring up, silicon debug, and characterization execution across PVT corners.
• Analyze yield, performance distributions, and device failures; lead root cause analysis and drive corrective actions across global teams.
• Perform circuit sensitivity analysis, interpret findings, and guide deep dive investigations to resolution.
• Drive innovation in SoC test, debug, DFT, and test methodology, translating ideas into production ready solutions.

Production & Cost Optimization

• Own test content optimization to meet product quality and cost targets.
• Drive yield, test time, and margin improvements from wafer sort through backend test.
• Partner with manufacturing and quality teams to ensure stable, scalable production.

PREFERRED EXPERIENCE:

Technical

• Strong hands-on experience supporting complex SoC products (e.g., mobile or automotive processing units).
• Proven technical leadership across at least one full SoC product lifecycle (pre silicon to production).
• Deep expertise in DFT and ATE test methodologies, spanning areas like ATPG Scan, MBIST, Functional, and High‑Speed IO testing across complex SoC environments.
• Strong experience with Advantest 93k/Teradyne test platforms.
• Solid understanding of CPU / GPU / SoC architectures with system level interactions as a plus.
• Strong programming or scripting skills (Python, C/C++, Perl, Java).
• Experience with industry EDA tools (Mentor, Synopsys, Cadence) is a plus.

Leadership

• Demonstrated ability to act as a technical decision‑maker and mentor within the test organization.
• Strong communication skills to engage deeply with global, cross‑functional engineering teams.
• Willingness and capability to take on broader ownership, including mentoring engineers and contributing to long‑term test strategy and team development.
• Strong ability to lead by influence
• Ability to program manage and drive test schedules and deliverables

ACADEMIC CREDENTIALS:

• Bachelor/Master in Electrical/Electronic Engineering