Engineer, System Design Engineering
2 months ago
Develop, integrate, and debug Verification IP (VIP) for industry‑standard protocols (e.g., PCIe or similar)Perform VIP‑based simulation using Siemens.....
- Develop, integrate, and debug Verification IP (VIP) for industry‑standard protocols (e.g., PCIe or similar)
- Perform VIP‑based simulation using Siemens Questa / Questa Advanced Simulator
- Configure, customize, and maintain Avery VIPs (or equivalent) for block‑level, subsystem, and SoC‑level environments
- Build and maintain SystemVerilog / UVM testbenches
- Analyze functional coverage, assertions, and protocol compliance results
- Debug complex simulation failures using waveform analysis, assertions, and protocol checkers
- Collaborate with RTL designers to identify, root‑cause, and resolve functional issues
- Support regression infrastructure and improve simulation efficiency and stability
- Contribute to verification methodology, best practices, and reusable VIP components
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