Total 10 job vacancies by Sandisk

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• As a Packaging Engineer, you will work in the Packaging R&D group on thermal designs across semiconductor packaging level, flash product printed circuited board assembly (PCBA) level, and host level.
• The ideal candidate will be responsible for thermal modeling (CFD) and validation of flash products PCBA using analytical/numerical analysis and measurement techniques.
• The focus will be on solutions to meet increased demands for small form factor packages with constrained physical and thermal environments.

We're looking for a hands-on Creative Producer to join our dedicated NPI production team. You'll own the full marketing asset production cycle - from concepting and planning through to final delivery - while also bringing a strong design eye to branded visual content. This is a great fit for someone who is equally comfortable on set and in Adobe Creative Suite.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Interpret creative briefs and lead internal brainstorming sessions to shape compelling visual concepts, presenting storyboards, mood-boards, and supporting design assets to stakeholders for alignment and buy-in. 
• Manage the full pre-production approval process across internal teams, before briefing external vendors and aligning on all production logistics including locations, talent, product samples, costings, and ensuring compliance with company policy on rights, licenses, and release documentation. 
• Manage video and photo shoots, ensuring storyboard frames, talent performance, scene composition, product representation, and location treatments are executed in full accordance with the approved creative and brand guidelines. 
• Review vendor-submitted edits with the internal team, ensuring all post-production elements — animation, titles, supers, and graphic elements — are compliant with brand guidelines. 
• Own the end-to-end approval process, managing all feedback loops and revision rounds with the vendor until sign-off is obtained, before overseeing final asset delivery in the correct formats and maintaining organized libraries of all production files. 

• Need to work in collaboration with global analog teams across sites.
• Will be responsible for driving innovation in Analog IP designs.
• Responsible for design of IPs like Voltage regulators, LDO, Current and Voltage reference, High Voltage charge pumps, temperature sensors, oscillators etc using industry standard EDA tools.
• Should provide technical leadership and mentor junior engineers.
• Responsible for developing processes and robust design methodology.
• Help build overall competency in Analog domain.

Key Responsibilities – Mask Design Technologist

• Layout Design & Optimization: Develop and optimize peripheral and core circuit layouts for Analog, Digital, and Mixed-signal domains, ensuring adherence to design specifications, performance requirements, and foundry rules.

• Design Verification: Perform DRC (Design Rule Check) and LVS (Layout Versus Schematic) verification, parasitic extraction, and sign-off methodologies to guarantee design integrity and first-pass success.

• Power Distribution & Floorplanning: Analyze and implement full-chip power distribution strategies and floorplanning optimization to ensure efficient electrical performance, minimize parasitics, and reduce die size.

• Cross-Functional Collaboration: Work closely with design and process engineering teams across multiple sites to resolve issues, align methodologies, and drive project success while maintaining high standards of accuracy and consistency.

In this senior leadership role, you will lead the development of advanced mask layouts for next-generation memory technologies, strengthening our company’s position as a leader in the semiconductor industry.

• We are seeking a Staff Engineer, who understand embedded NAND system design and firmware algorithms in order to create a test validation plans and implement them in modern object oriented languages.
• Work closely with the system architects and the firmware team to develop Validation plans, test bench and test cases
• Develop an overall validation strategy including defining validation infrastructure and validation methodology
• Debug the firmware and expose design issues
• Define and design functional tests required to meet customer needs
• Review SanDisk UFS/eMMC embedded NAND validation requirements and influence future SanDisk product design for debug and test
• Work with customers to understand field bugs and to enhance the validation coverage
• Interface with all key stakeholders to ensure product validation meets customer expectations and needs

Job Description: 

• Should be good in understanding the PCB board’s w.r.t layout schematics and information about the various active and passive components on the PCB.
• Good hands on BOM analysis and report preparation.
• Excellent debugging and Failure Analysis skills with exposure to tools like protocol analysers, Logical analysers, CRO etc. Should be good at reproducing and root causing the issues.
• Good Power analysis and Power tree Distribution Reverse engineering skills
• Good to have Experience in Storage Domain.
• Good to have Knowledge on the PCB Construction and Assembly details
• Good Experience in System level activities for hardware design and validation.
• Good to have Experience working with Flash memory technologies and internals.
• Good to have Experience in NVMe, SD/uSD, USB or PCIE protocols understanding.
• Mindset towards delivering the Highest Quality product to the customer.
• Must be execution focused, have zeal to learn more and do more. Take initiatives.
• Proven ability to achieve results in a fast moving, dynamic environment.
• Should be good team player, approachable with to do attitude.

Job Description: 

• Should be good in understanding the PCB board’s w.r.t layout schematics and information about the various active and passive components on the PCB.
• Good hands on BOM analysis and report preparation.
• Excellent debugging and Failure Analysis skills with exposure to tools like protocol analysers, Logical analysers, CRO etc. Should be good at reproducing and root causing the issues.
• Good Power analysis and Power tree Distribution Reverse engineering skills
• Good to have Experience in Storage Domain.
• Good to have Knowledge on the PCB Construction and Assembly details
• Good Experience in System level activities for hardware design and validation.
• Good to have Experience working with Flash memory technologies and internals.
• Good to have Experience in NVMe, SD/uSD, USB or PCIE protocols understanding.
• Mindset towards delivering the Highest Quality product to the customer.
• Must be execution focused, have zeal to learn more and do more. Take initiatives.
• Proven ability to achieve results in a fast moving, dynamic environment.
• Should be good team player, approachable with to do attitude.

• Research and implement innovative ways to test/validate PCIe/NVMe SSD’s.
• Work with cross-functional teams for POC and architecture discussions for validation infrastructure.
• Creating and maintaining technical and process documents.
• Develop device driver, critical framework, modules on top of Real time OS
• Work in peripherals like USB, PCIe, advanced serial interfaces for Infrastructure

• Develop, integrate, and debug Verification IP (VIP) for industry‑standard protocols (e.g., PCIe or similar)
• Perform VIP‑based simulation using Siemens Questa / Questa Advanced Simulator
• Configure, customize, and maintain Avery VIPs (or equivalent) for block‑level, subsystem, and SoC‑level environments
• Build and maintain SystemVerilog / UVM testbenches
• Analyze functional coverage, assertions, and protocol compliance results
• Debug complex simulation failures using waveform analysis, assertions, and protocol checkers
• Collaborate with RTL designers to identify, root‑cause, and resolve functional issues
• Support regression infrastructure and improve simulation efficiency and stability
• Contribute to verification methodology, best practices, and reusable VIP components

• Work as one of  the senior team members or as lead of analog IPs and deliver analog blocks on-time with state-of-the-art architecture to meet the overall product requirements
• Work closely with team in designing and delivering analog blocks
• Design analog modules from scratch
• Handling assigned tasks independently
• Pro-actively get design issues/problems resolved
• Contribute to or propose innovative design solutions and design methodologies
• Work closely with the layout engineers on providing requirements and guidelines