Total 51 job vacancies by Sandisk

We're looking for an experienced Senior Manager to lead our Memory Reliability & Qualification engineering organization in Bengaluru, India. In this strategic leadership role, you will oversee the complete NAND Flash memory qualification lifecycle, drive innovation, and build a high-performing engineering team. You will be responsible for translating business objectives into technical strategies while maintaining operational excellence and delivering world-class solutions.

• Lead and mentor a team of NAND Technology Reliability engineers, fostering a culture of innovation, collaboration, and continuous improvement
• The candidate should have a vast experience in semiconductor industry along with strong skills in Failure Analysis, Root Cause Analysis, Device Physics and programming
• Develop and execute memory qualification strategies aligned with organizational goals and business demands
• Oversee the complete qualification lifecycle, from requirements gathering through successful memory qualification, ensuring timely delivery and attention to details
• Manage engineering budgets, resource allocation, and project timelines to optimize operational efficiency
• Make critical technical decisions based on the performance and reliability checkpoint data to judge the memory technology
• Collaborate with cross-functional teams including product engineering, test engineering and product management to ensure seamless delivery
• Develop and implement performance metrics to track engineering team productivity and deliverables quality
• Represent the team in executive meetings and strategic planning sessions

• Providing technical leadership and expertise to define requirements for framework through programming/scripting of verification and emulation flows.
• Partnering with ASIC engineers to deploy and support framework for technologies like advanced verification environment configuration and management.
• Collaborating cross-functionally to optimize verification and emulation workflows and standardize methodologies.

• Need to work in collaboration with global analog teams across sites.
• Will be responsible for driving innovation in Analog IP designs.
• Responsible for design of IPs like Voltage regulators, LDO, Current and Voltage reference, High Voltage charge pumps, temperature sensors, oscillators etc using industry standard EDA tools.
• Should provide technical leadership and mentor junior engineers.
• Responsible for developing processes and robust design methodology.
• Help build overall competency in Analog domain.

Key Responsibilities – Mask Design Technologist

• Layout Design & Optimization: Develop and optimize peripheral and core circuit layouts for Analog, Digital, and Mixed-signal domains, ensuring adherence to design specifications, performance requirements, and foundry rules.

• Design Verification: Perform DRC (Design Rule Check) and LVS (Layout Versus Schematic) verification, parasitic extraction, and sign-off methodologies to guarantee design integrity and first-pass success.

• Power Distribution & Floorplanning: Analyze and implement full-chip power distribution strategies and floorplanning optimization to ensure efficient electrical performance, minimize parasitics, and reduce die size.

• Cross-Functional Collaboration: Work closely with design and process engineering teams across multiple sites to resolve issues, align methodologies, and drive project success while maintaining high standards of accuracy and consistency.

In this senior leadership role, you will lead the development of advanced mask layouts for next-generation memory technologies, strengthening our company’s position as a leader in the semiconductor industry.

In this position, the individual will be responsible for design & development of device FW for next-generation PCIe / NVMe SSD products.

Responsibilities:

• Design, implement, debug firmware for the next generation of SSDs
• HW Interface drivers, algorithm design and implementation
• Contribute to the SSD firmware and play a significant role in delivering next generation SSDs to market
• Design and implement firmware algorithms needed to achieve best in class performance goals
• Support failure analysis on test systems
• Active participation in technical design, implementation reviews across teams and functions

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Represents Package Engineering in cross-functional teams and ensures that packages are characterized, qualified, and introduced into production in a timely manner while meeting all mechanical, electrical, performance, reliability, and quality requirements.        
• Lead cross-functional teams, factories, and other engineers while managing the entire package life cycle process.          
• Works with the Packaging R&D teams worldwide to develop and qualify new and emerging packaging technology required to support business needs
• Support assembly yield improvement and package cost reduction programs.  
• Lead new product from low volume to high volume production transition with yield and quality meeting goals. Ensure FMEA, SOD, Control Plan, recipe guideline, SPC and other assembly controls are ready prior to high volume production.
• Work on innovative ideas for best-in-class package design.

We are seeking a highly skilled and experienced Principal Engineer, Product Development Engineering to join our team in Central Seberang Perai, Malaysia. In this pivotal role, you will work in driving innovation for our product development processes,engineering and design.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Spearhead the development and implementation of advanced engineering strategies to enhance product performance and efficiency
• Analyze and interpret data to drive informed decision-making in product development processes
• Collaborate with stakeholders to define product requirements and ensure alignment with business objectives
• Mentor and guide junior engineers, fostering a culture of innovation and continuous improvement
• Develop and maintain technical documentation, including design specifications and engineering standards
• Evaluate and implement new technologies and methodologies to improve product development processes
• Ensure compliance with industry standards and regulations throughout the product development lifecycle
• Participate in technical reviews and provide expert guidance on module engineering challenges
• Drive cost reduction initiatives while maintaining product quality and performance

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Responsible on execution and analysis of NAND memory reliability qual and perform Failure Analysis.
• Designing and developing reliability sequences for given technology node in addition to performing actual reliability test execution followed by Failure Analysis to root cause the issues reported.
• Some of the other areas that this position will include will be: R&D support, DPPM improvement, test documentation, comprehension of design manuals and data sheets, using various bench equipment (oscilloscopes, logic analyzers, multimeter), and interacting with other engineering groups.

• Development of C++/SystemC models for complex ASIC IPs, SOCs and Flash Memories.
• Create System Level Tests and/or Standalone Unit Tests and verify the models.
• Lead and Guide team in the project activities.
• Keen on schedule and quality of the deliverables.
• Timely support to the stakeholders enabling software bring-up.

We are seeking an experienced and proactive Senior Cyber Security Engineer to join our Global Cyber Security Operations team. This role requires an experienced security professional responsible for executing and supporting cybersecurity operations globally but with a focus on our manufacturing facility. This role has a primary focus on global insider risk management and data loss prevention (DLP), while also providing hands‑on operational support for local manufacturing risks. You will work closely with our Security Operations Center (SOC), incident response teams, and other IT stakeholders to stay ahead of emerging threats and ensure we’re able to build great products securely.

ESSENTIAL DUTIES AND RESPONSIBILITIES: 

Insider Risk Management & Data Protection

• Assist in the management and configuration of Sandisk governance controls related to data security
• Execute day‑to‑day operations of insider risk management and data security controls using Microsoft Purview, MIP, IRM, and DLP technologies.
• Monitor, triage, and investigate insider risk alerts and data loss events using Microsoft Purview, Microsoft Defender, and SIEM tooling, following defined procedures and escalation paths.
• Conduct detailed analysis and documentation of insider risk and data protection incidents, including evidence handling and recommended follow‑up actions.
• Support tuning and refinement of DLP and insider risk policies to improve signal quality and reduce false positives, in coordination with platform owners and senior analysts.

Endpoint Detection, Response & Manufacturing Security

• Perform hands‑on monitoring, investigation, and response activities using Microsoft Defender for Endpoint and CrowdStrike Falcon in an enterprise environment.
• Investigate endpoint‑based alerts affecting manufacturing office systems, engineering workstations, and privileged users, correlating activity across EDR, identity, and data signals.
• Support incident response efforts impacting the manufacturing site, including containment actions, evidence collection, and post‑incident documentation.
• Maintain awareness of manufacturing‑specific risks, including engineering workflows, shared systems, and IP‑sensitive environments.

Automation, Scripting & Analysis

• Use scripting and basic programming to support investigations, data analysis, and operational efficiency.
• Develop and maintain simple scripts or queries (e.g., PowerShell, Python, KQL) to assist with alert triage, log analysis, data validation, and reporting.
• Leverage scripting to reduce repetitive manual tasks while operating within established security tooling and change controls.

Work Style & Attributes

• Self‑motivated and dependable, with a strong work ethic in an on‑site, semi‑isolated environment.
• Comfortable operating as an individual contributor with defined scope and responsibilities.
• Collaborative and approachable, with a service‑oriented mindset toward local manufacturing and IT teams.
• Detail‑oriented and risk‑aware, with an appreciation for balancing security controls against manufacturing uptime and business impact.
• Strong analytical and critical-thinking skills with high attention to detail.
• Clear and concise written and verbal communication, including to non-technical stakeholders.
• Ability to remain composed and effective under pressure during active security incidents.
• Team-oriented and collaborative with a proactive, security-first mindset.
• Ability to approach security challenges with genuine curiosity and a questioning attitude, consistently digging deeper to understand the "why" behind alerts, behaviors, and anomalies rather than accepting surface-level conclusions.

As a Pricipal Emulation Engineer in the ASIC Emulation team, you will be responsible for Emulation builds, sanity test suite & methodology. 

• Providing technical leadership and expertise to define requirements for Emulation and Emulation IP development.
• Create emulation models from RTL / Netlist. Develop hardware collateral to be integrated with the Palladium / FPGA emulation mode.
• Experience in Palladium or Zebu Platforms Automation and increase process efficiencies.
• Collaborating cross-functionally to optimize emulation workflows and standardize methodologies.
• Work with extended teams to debug environment and drive cross-functional testing (Firmware, Software, Verification and Design)
• Triage failures with design, verification, firmware, software teams.
• Mentoring and guiding junior engineers, fostering a culture of collaboration, innovation and continuous improvement.

Skills Required:

• Working knowledge of Linux/Unix environment and shell scripting
• Excellent debugging and problem-solving skills with simulation and emulation environments.
• Cross-Functional Collaboration: Ability to work closely with design, validation, firmware, and physical design teams to resolve system-level issues.
• Strong team player, able to collaborate effectively across architecture, design, and validation teams.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Good discipline and behavior, willing to learn and grow.
• Responsible for Equipment Engineering KPI which is MTBA, OEE, machine downtime, Quality and Preventive maintenance.
• Ability to support on hardown machines and assist technician to troubleshoot the machine.
• Ability to support on machines improvement in term of productivity and quality.
• "This role requires reliable presence to support operational and team objectives. Employees are expected to maintain regular attendance aligned with the company’s work schedule."

We are looking for a Front‑End PCIe Firmware Engineer to design, develop, and maintain the device‑side PCIe Front‑End firmware stack for next‑generation high‑performance storage controllers. In this role, you will own key layers of the PCIe firmware responsible for link bring‑up, configuration space management, MMIO, interrupts, DMA, and command/queue handling, working closely with hardware, validation, and host‑software teams.

Key Responsibilities

• PCIe Front‑End Firmware Development

  • Design and implement firmware for PCIe initialization, link bring‑up, and configuration space programming (BARs, capabilities, MSI/MSI‑X).
  • Develop MMIO‑based control and status interfaces used by host software.
  • Work closely with DMA engines to enable high‑bandwidth, low‑latency host‑to‑device and device‑to‑host data transfers. 

• Architecture & Cross‑Functional Collaboration

  • Collaborate with hardware design teams on PCIe IP integration and bring‑up.
  • Partner with validation teams on FPGA, emulation, and ASIC debug.
  • Work with host‑side driver and system software teams to define clean, scalable interfaces. 

• Debugging & Performance Optimization

  • Debug complex system‑level issues spanning firmware, hardware, and host.
  • Profile and optimize PCIe throughput, latency, and interrupt efficiency.
  • Support bring‑up on pre‑silicon and post‑silicon platforms.

• We are seeking a Staff Engineer, who understand embedded NAND system design and firmware algorithms in order to create a test validation plans and implement them in modern object oriented languages.
• Work closely with the system architects and the firmware team to develop Validation plans, test bench and test cases
• Develop an overall validation strategy including defining validation infrastructure and validation methodology
• Debug the firmware and expose design issues
• Define and design functional tests required to meet customer needs
• Review SanDisk UFS/eMMC embedded NAND validation requirements and influence future SanDisk product design for debug and test
• Work with customers to understand field bugs and to enhance the validation coverage
• Interface with all key stakeholders to ensure product validation meets customer expectations and needs

We are seeking an experienced Firmware Engineering Program Manager (EPM) to drive execution excellence across complex firmware development programs. This role partners closely with Firmware Engineering, Validation, Architecture, and Cross‑Functional stakeholders to ensure predictable delivery, risk management, and transparent execution across multiple concurrent firmware projects.

The ideal candidate brings strong program management fundamentals combined with working knowledge of firmware / embedded systems, enabling effective engagement with engineering teams and leadership.

Key Responsibilities

Program & Delivery Management

• Own end‑to‑end project execution for one or more firmware programs, from planning through release.
• Build and maintain integrated project plans covering firmware development, validation, integration, and release milestones.
• Drive milestone tracking, dependency management, and timely escalation of risks and issues.
• Ensure delivery commitments are met in terms of schedule, scope, and quality.

Execution Tracking & Reporting

• Establish and maintain execution dashboards using JIRA, dashboards, EasyBI, SmartSheets, or similar tools.
• Track sprint execution, feature progress, defect trends, validation readiness, and release health.
• Prepare clear, concise management summaries for senior leadership reviews.
• Ensure action items from reviews and interlocks are tracked to closure.

Stakeholder & Cross‑Functional Coordination

• Act as the primary execution interface between Firmware Engineering, Validation, Hardware, System, Product, and Operations teams.
• Drive regular interlocks, syncs, and reviews to align on priorities, risks, and mitigation plans.
• Facilitate effective communication across geographically distributed teams.

Process & Operational Excellence

• Support adoption of Agile / Scrum like execution models within firmware teams.
• Help standardize execution practices, reporting formats, and release readiness criteria.
• Identify execution gaps and continuously improve planning, tracking, and reporting mechanisms.

Budget & Resource Tracking

• Support budget consolidation, spend tracking, and forecasting for firmware programs.
• Track contractor/vendor engagement, PO execution, and alignment with financial plans.
• Ensure timely execution of staffing and resource requests