Total 5 job vacancies by Marvell Asia Pte Ltd

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and at least 5+ years of related professional experience or Master’s degree in Computer Science, Electrical Engineering or related fields with 3+ professional experience.
• Deep understanding of layout methodology from initial chip planning to tape-out and parasitic optimizing in layout
• Experience in advanced process technology and Fin-FET is preferred
• Have a high level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports
• Possess high-level proficiency/knowledge of Synopsys or CADENCE layout entry tools
• Programming skills in any of the following are a plus: Skill or Ample or Perl, etc.
• Strong technical and analytical background, problem solving skills, etc.
• The candidate must have a proven record of laying out high-performance analog circuits in state-of-the-art CMOS process technologies, successfully performed top-level integrations, and placed products into volume production multiple times.
• Proficient in spoken and written English

Job Responsibilities

• Working with global teams across Argentina, Singapore, the U.S., and Europe, you will run simulations and verifications using Cadence Virtuoso, collaborating closely with the designer to refine and debug iteratively until the design meets specifications. Project durations vary from a few months to a year and a half with flexibility to switch based on changing priorities is appreciated
• Regular meetings with your paired designer ensure collaborative information sharing, integral to Marvell's commitment to partnership and teamwork.
• Key contributor and crucial role in the project lifecycle, participating in routine meetings as a technical mentor, layout team, and the broader project team.
• Provide updates on progress and may involve presenting specific issues or solutions encountered during the development of cutting-edge technologies
• Continuous learning and knowledge-sharing among colleagues

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and at least 8+ years of related professional experience or Master’s degree in Computer Science, Electrical Engineering or related fields with 5+ professional experience.
• Deep understanding of layout methodology from initial chip planning to tape-out and parasitic optimizing in layout
• Experience in advanced process technology and Fin-FET is preferred
• Have a high level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports
• Possess high-level proficiency/knowledge of Synopsys or CADENCE layout entry tools
• Programming skills in any of the following are a plus: Skill or Ample or Perl, etc.
• Strong technical and analytical background, problem solving skills, etc.
• The candidate must have a proven record of laying out high-performance analog circuits in state-of-the-art CMOS process technologies, successfully performed top-level integrations, and placed products into volume production multiple times.
• Proficient in spoken and written English

Job Responsibilities

• Working with global teams across Argentina, Singapore, the U.S., and Europe, you will run simulations and verifications using Cadence Virtuoso, collaborating closely with the designer to refine and debug iteratively until the design meets specifications. Project durations vary from a few months to a year and a half with flexibility to switch based on changing priorities is appreciated
• Regular meetings with your paired designer ensure collaborative information sharing, integral to Marvell's commitment to partnership and teamwork.
• Key contributor and crucial role in the project lifecycle, participating in routine meetings as a technical mentor, layout team, and the broader project team.
• Provide updates on progress and may involve presenting specific issues or solutions encountered during the development of cutting-edge technologies
• Continuous learning and knowledge-sharing among colleagues

Requirements

• Bachelor’s degree in Electrical Engineering or related field with 8+ years of experience. Master’s or PhD with 5+ years of experience preferred.
• Strong understanding in analog circuit design especially the following will be highly considered.
• High Speed Serdes' input matching network, semiconductor device physics and analog blocks (regulators, amplifiers, filters, transceivers).
• Good proficiency in ESD/Latchup standards and protection techniques, EDA tools (e.g., Cadence Virtuoso, Spectre, SPICE) and design rules for advanced process nodes

Job Responsibilities

• Architect and implement ESD protection schemes for high-speed analog and mixed-signal IP.
• Review circuit and layout designs, perform simulations, and ensure compliance with ESD standards.
• Collaborate with IP designers to mitigate ESD risks while preserving analog performance.
• Work on leading-edge nodes including 3nm FinFET and 2nm GAA technologies.

Requirements

• Completed a MS in Electrical Engineering with 8+ years of related experience or PhD degree in Electrical Engineering with 4+ years of related experience
• Hands-on experience in designing mixed signal circuits including ADCs, DACs, RX, TX, PLLs, Filters, Bandgap bias circuits, regulators, and other analog circuits.
• Specialized depth and/or breadth of expertise.
• Ability to apply innovative solutions to resolve complex issues.
• History of identifying and developing best practices that deliver high-quality and effective solutions.
• Strong knowledge on the deep sub-micron CMOS technologies.
• Knowledge and experience on low power and high-speed design techniques.
• Excellent problem solving and analytical skills.
• Strong knowledge on IC design CAD tools such as Spectre, Spice, Matlab, Hsim, Verilog, etc.
• Lab testing skills to evaluate the prototype unit to the design specification.

Job Responsibilities

• Work with multi-functional teams to deliver high-speed optical and electrical SerDes products.
• Define specifications based on link budget, behavioral modeling, and transistor-level feasibility.
• Drive schematic design and collaborate on mask design for implementation.
• Drive designs into high quality volume production with the team.

Company Overview

Marvell first revolutionized the digital storage industry by moving information at speeds never thought possible. Today, that same breakthrough innovation remains at the heart of the company’s storage, network infrastructure, and wireless connectivity solutions. With leading intellectual property and deep system-level knowledge, Marvell's semiconductor solutions continue to transform the enterprise, cloud, automotive, industrial, and consumer markets.

Job Summary

You will collaborate with global teams to run simulations and verifications using Cadence Virtuoso, driving iterative design refinement and debugging to meet specifications. You will contribute as a technical mentor and key team member throughout the project lifecycle, supporting the development of advanced semiconductor technologies.

Responsibilities

• Lead simulations and verifications using Cadence Virtuoso to validate design specifications and performance
• Collaborate closely with designers to iteratively refine and debug designs, ensuring alignment with project requirements
• Manage project tasks across varying durations, adapting to shifting priorities and resource allocation
• Facilitate regular meetings with paired designers to share information and foster teamwork aligned with Marvell’s partnership values
• Participate actively in project lifecycle activities including progress updates, technical mentoring, and presenting solutions to complex design challenges
• Apply expertise in CAD tools to implement microelectronic and implementation layers beyond schematic design
• Deliver high-speed or precision analog circuit designs across multiple process nodes, ensuring quality and performance standards
• Oversee end-to-end development stages from cell design to functional blocks, macros, and full chip interfaces
• Communicate effectively with global teams to coordinate tasks and resolve technical issues