Total 704 engineering job vacancies in Singapore

Step into a career with ASM, where cutting edge technology meets collaborative culture. ​

For over 55 years ASM has been ahead of what’s next, at the forefront of innovation and what’s technologically possible. With more than 4,500 ASMers representing 70 nationalities, our people and our advanced semiconductor devices are playing a crucial role in trends such as 5G, cloud computing, AI, and autonomous driving.  But we’re more than just a tech company. We value diversity, inclusion and sustainability as we strive to make a positive impact on the world.  Our development programs help support your growth, shaping your future and pushing the boundaries of innovation to unleash potential.  

Job's mission

Join ASM’s Advanced Packaging team and lead the design and development of next-generation semiconductor process equipment. In this role, you will shape system architecture, drive automation strategies, and collaborate across functions to deliver innovative solutions. Your expertise will ensure projects meet the highest standards of safety, quality, and performance.

What you will be working on

• Lead design and development of semiconductor vacuum systems, including equipment selection, process controls, and automation integration.
• Develop and implement automation strategies using PLCs, SCADA, and related tools to optimize efficiency.
• Manage project timelines, budgets, and resources while ensuring compliance with safety and quality standards.
• Collaborate with cross-functional teams in manufacturing, operations, and quality to align on goals and deliverables.
• Provide technical support and troubleshooting for equipment and automation systems, driving root cause analysis and resolution.
• Own BOM release and maintenance, ensuring accurate documentation and reporting for stakeholders.
• Drive continuous improvement initiatives and stay current with industry trends and emerging technologies.
• Apply engineering principles and research data to create designs for semiconductor systems and products.
• Perform engineering calculations for structural, thermal, and fluid dynamics challenges.
• Create and revise CAD models and detailed drawings using Creo Parametric for components and assemblies.
• Prepare comprehensive design documentation for manufacturing and testing of prototypes and production products.

What we are looking for

• Bachelor's, Master’s or PhD in Mechanical Engineering or related field.
• Minimum 8 years of experience in semiconductor equipment design, development, and automation.
• Expertise in complex mechanical systems such as reactors, vacuum chambers, gas delivery systems, pneumatics, and cooling circuits.
• Strong analytical and problem-solving skills with ability to lead innovative design concepts.
• Experience with PLC programming and revision control tools such as Git.
• Ability to work independently and collaboratively in a team environment.

What sets you apart

• Experience with semiconductor capital equipment and metal deposition products.
• Knowledge of CE, NFPA, Semi S2-95, and other relevant standards for semiconductor manufacturing equipment.
• Familiarity with materials including metals, plastics, coatings, and finishes.
• Proficiency in Microsoft applications, CREO, and AutoCAD.
• Knowledge of ASME Y14.5 and/or ISO 1101:2017 geometric dimensioning and tolerancing.
• Strong communication skills to present design concepts effectively to peers and management.
• Ability to manage multiple priorities and meet aggressive deadlines while maintaining quality standards.

Apply today to be part of what’s next.

We make the tech that enables the chips in devices which improve lives around the world. We do this with an eye to the future, pushing the boundaries of what’s possible through cutting-edge innovation, and driving the next wave of technological breakthroughs that shape how we live, work, and connect.

To learn more about ASM, find us at asm.com and on LinkedIn, Facebook, Instagram, X and YouTube.

ASM is an equal opportunity employer and considers qualified applicants for employment without regard to race, color, religion, age, nationality, social or ethnic origin, sexual orientation, gender, gender identify or expression, marital status, pregnancy, political affiliation, disability, genetic information, veteran status, or any other characteristic protected by law.

About Cynapse 

Cynapse is a leading Agentic AI software company specializing in enterprise-grade Video Intelligence Solutions Powered by Agentic AI, tailored to meet the unique challenges of various industries. Our vertical-specific solutions empower organizations to enhance safety, operational efficiency, and security in complex environments such as roads, seaports, airports, and cities. 

Led by a global team with a proven track record of scaling startups into market leaders, we foster innovation, collaboration, and diverse perspectives. Headquartered from US, Cynapse serves clients worldwide, redefining what’s possible with video intelligence. 

Job Description 

We are looking for a Junior to Mid-Level Machine Learning Engineer to join our Model Engineering Team. This role is intended for engineers who view models as systems to be understood, developed, and improved rather than simply consumed as black-box components.

You will contribute across the full model lifecycle, from dataset preparation and architecture development to training, evaluation, and optimisation. Working closely with experienced engineers, you will improve model performance through experimentation, data-centric approaches, and systematic analysis, helping to build robust and efficient computer vision systems for real-world applications.

What You’ll Do: 

• Train, fine-tune, and evaluate computer vision models for tasks such as classification, object detection, segmentation, pose estimation, and action recognition.
• Contribute to model development through architecture enhancements, custom heads, loss functions, and training strategy optimisation.
• Design and execute experiments to evaluate model improvements and performance trade-offs.
• Prototype, benchmark, and assess new architectures, techniques, and approaches against established baselines.
• Investigate edge cases and performance limitations, and improve model accuracy, robustness, and efficiency.
• Consider practical constraints such as latency, throughput, resource efficiency, and hardware-specific optimisation.
• Collaborate with engineering teams to improve dataset quality, model performance, and system reliability.

Requirements 

• Bachelor’s degree in Computer Science, Artificial Intelligence, Machine Learning, Data Science, or a related technical field.
• At least 2 years of hands-on experience training, fine-tuning, and evaluating computer vision models through academic, project, internship, or professional work.
• Hands-on experience with PyTorch and/or TensorFlow.
• Proficiency in Python and familiarity with Linux environments and command-line tools.

Bonus Skills 

• Experience modifying models beyond high-level APIs (e.g. custom heads, backbone modifications, loss functions, or training pipelines).
• Exposure to multimodal, vision-language, foundation, or open-vocabulary models.
• Experience with optimisation techniques such as quantisation, pruning, distillation.
• Familiarity with experiment tracking, reproducibility, or MLOps practices.

Personal Competencies 

• Strong interest in understanding how model architectures, data quality, and training strategies influence performance.
• Enjoy experimentation, performance analysis, and iterative model improvement.
• Eager to take ownership of model components and grow into increasingly complex model development responsibilities.

Note: Due to the nature of the role, the position is considered only for candidates who are already based in Singapore.

The School of Chemistry, Chemical Engineering and Biotechnology (CCEB) at NTU Singapore, in collaboration with Wageningen University & Research (WUR), is part of Singapore Indoor Farming System (SingFarm)—a CREATE-NRF programme focused on building a sustainable, data-driven food production model with strong industry relevance to contribute Singapore’s ambition in achieving 20 per cent local production of its fiber (vegetables, mushrooms etc.) by 2035. The candidate would be working in a multinational team at the forefront of Singapore’s agricultural innovation and food security.

The successful candidate will work in Work Package 3.3: Urban Demo Lab. In this role, you help translate research results from across the program into demonstrators and settings for collaborative exploration that allow key stakeholders to engage with emerging food production technologies – and each other. The Urban Demo Lab serves as a platform where researchers, industry partners, and other stakeholders explore applications, provide critical design feedback and identify opportunities for further innovation: it serves as an attractor for future projects and strategic alliances that maximize the urban impact of ongoing research and development.

As an innovation facilitator, your work provides the active interface that is needed between research, technology translation, and stakeholder engagement. By stimulating dialogue and collaborative learning, you identify critical friction zones and promising ways forward, effectively accelerating the uptake of scientific innovations in real-world applications.

Key Responsibilities:

• Collaborate with research teams to identify key elements of research suitable for demonstration.

• Facilitate workshops, meetings, and stakeholder sessions to explore research outcomes, gather feedback, and identify innovation opportunities.

• Translate scientific insights into demonstrators, prototypes, or other formats such as an overall performance dashboard that communicate application potential to diverse audiences.

• Contribute to identifying and engaging potential partners or funders interested in further development of promising ideas.

Job Requirements:

• Completed PhD in a relevant field (e.g., food systems, food production, sustainability transitions or related fields).

• Systems thinker with an interest in innovation in food production and controlled environment agriculture

• Experience translating scientific research into practical applications, demonstrators or stakeholder-facing outputs.

• Excellent communication skills and ability to work across disciplinary and organizational boundaries.

• Experience facilitating interdisciplinary collaboration, workshops, or stakeholder engagement is an advantage.

We seek a diverse and inclusive workforce and is committed to equality of opportunity. We welcome applications from all and recruit on the basis of merit, regardless of age, race, gender, religion, marital status and family responsibilities, or disability.

We regret that only shortlisted candidates will be notified.

Join a Leading Engineering & Infrastructure Organisation

We are looking for passionate and driven Engineering graduates and professionals to join a reputable organization supporting critical infrastructure and engineering operations in Singapore.

Why Join Us?

• Gross Salary : Up to $5,000+++ per month

• Monthly AWS allowance

• Generous performance bonus of up to 3 months

• Starting 18 Days Annual Leave

• Family and Childcare Leave entitlement

• Structured training and career progression opportunities

• Stable career with long-term growth prospects

Key Responsibilities

• Support engineering operations, maintenance, and improvement initiatives.

• Conduct troubleshooting, investigations, and root cause analysis of engineering issues.

• Analyse system performance data and recommend reliability improvements.

• Assist in engineering projects, testing, commissioning, and asset enhancement activities.

• Prepare technical reports, documentation, and work instructions.

• Collaborate with cross-functional teams to improve operational performance and safety standards.

• Ensure compliance with engineering, quality, and safety requirements.
  

Requirements

• Bachelor's Degree in Mechanical Engineering, Electrical Engineering, Electronics Engineering, Mechatronics Engineering, or other relevant Engineering disciplines.

• Candidates with relevant engineering, maintenance, project, reliability, manufacturing, transportation, infrastructure, utilities, aerospace, marine, or industrial experience are encouraged to apply.

• Strong analytical and problem-solving skills.

• Good communication and interpersonal abilities.

• Ability to work independently and as part of a team.
  

Apply Now

If you are looking to kickstart or advance your engineering career with an established organization offering attractive compensation, strong career development, and excellent benefits, we would love to hear from you.

Submit your updated resume today for consideration.

Please send in your resume to :

edward.liau@cornerstoneglobalpartners.com or whatapp me at +65 96578518

Edward Liau Xianke R1217423

Cornerstone Global Partners

License Number: 19C9859

Principal Engineer / Manager, Defect Detection & Yield Engineering

Key Responsibilities

• Lead defect detection and yield improvement initiatives across semiconductor manufacturing operations.

• Drive root cause analysis and corrective actions for process and quality excursions.

• Analyze defect and yield data to identify trends and improvement opportunities.

• Partner with Process, Manufacturing, Quality, and Engineering teams to improve operational performance.

• Support implementation of advanced inspection and monitoring solutions.

• Develop best practices and mentor engineers within the organization.

Requirements

• Degree in Engineering, Materials Science, Physics, or related discipline.

• 7+ years of semiconductor manufacturing, yield, process, or defect engineering experience.

• Strong analytical, problem-solving, and stakeholder management skills.

• Experience in defect analysis, process monitoring, and yield improvement.

• Ability to lead cross-functional initiatives in a fast-paced environment.

Company Overview

AerOne Techniques is a team of aviation professionals committed to creating innovative solutions that inspire and empower. Join us to shape the future of aviation with global impact and cutting-edge expertise.

Job Summary

The Manager, Aviation Sales Engineering and Asset Management drives global commercial revenue by integrating aerospace engineering expertise with commercial asset strategy. This role leads international technical sales teams, manages global aviation asset lifecycles, and negotiates complex agreements with airlines, lessors, and MRO providers.

Responsibilities

• Define and implement technical sales strategies for international commercial airlines, lessors, and global MRO markets to drive revenue growth.
• Lead engineering teams to develop high-margin commercial proposals by translating technical capabilities into customer-focused solutions.
• Manage cross-border RFQ/RFP processes ensuring compliance with regional requirements to secure global contracts.
• Develop quantifiable total cost of ownership (TCO) models to demonstrate clear ROI to international customers.
• Execute global asset portfolio strategies optimizing lifecycle from acquisition through leasing, operations, to end-of-life teardowns.
• Perform data-driven asset valuation and analytics using cross-border technical records, utilization trends, and market data to inform decision-making.
• Mitigate technical risks and ensure asset compliance with global regulatory frameworks including FAA, EASA, CAAC, and CAA.
• Strategically deploy rotables, engines, and component inventory across international hub networks to maximize utilization.
• Mentor and lead diverse, remote, and cross-functional teams across Sales Engineering, Asset Management, and Technical Operations to achieve business goals.
• Analyze regional market trends to identify and pursue expansion opportunities in emerging global commercial aviation sectors.
• Build and maintain trusted advisor relationships with C-suite executives at global airlines and leasing firms to support business growth.

Required competencies and certifications

• Bachelor’s degree in Aerospace, Engineering, Aviation Management, or Finance.
• Minimum 10 years of progressive leadership experience in commercial aviation technical sales, MRO commercial management, or aircraft leasing.
• Proven experience managing multi-million-dollar international commercial deals, cross-border asset transfers, and global portfolios.
• Deep technical knowledge of commercial aircraft platforms (Boeing, Airbus) and global aviation regulatory authorities (FAA, EASA, etc.).
• Ability to travel internationally up to 70% to support global clients and asset inspections.

Preferred competencies and qualifications

• MBA or advanced technical degree.

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.
  

  Performs hardware, software, semiconductor design or telecomm engineering assignments. This job mapping should be used only if the position cannot be mapped specifically to other design/development engineering jobs.

Key Responsibilities:

• Carry out daily inventory store activities;
• Receive, inspect, and verify incoming materials, goods, and supplies against delivery documentation;
• Issue materials and products in accordance with authorized requests and record all stock movements;
• Work with inventory store manager-in-charge to review process workflow and implement process improvements to increase efficiency and effectiveness;
• Ensure safe, proper and effective housekeeping of inventory store;
• Issue items, update inventory and monitor stock levels;
• Manage disposal of waste and carry out regular inspections of inventory store items and storage conditions;
• Label, store and file stock items and ensure all required documentation are completed;
• Conduct regular stock takes, support reconciliation and compile necessary reports;
• Allocate storage space and ensure safe equipment handling at all times;
• Participate in innovation and work improvement projects;
• Perform any other duties as assigned.
  

The ideal candidate should preferably:-

• Possess at least Nitec/Higher Nitec qualifications; and
• Be willing to perform shift work.

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.

Job Summary

An opportunity for Head of Software Engineering to drive the design, implementation and delivery of one or more applications ensuring efficient, consistent and compliance execution of technology modernize systems / solutions. 

Ideal candidate should have technical knowledge and skills in system architecture and solutioning, technology deployment and operations to ensure technology platforms and solutions adhere to architecture standards for innovative initiatives as well as to drive high-impact modernization projects.

Mandatory Skill-set

• Degree in Information Technology, Computer Engineering, Computer Science or Information System;
• Minimum 10 years of experience in multi-squad development with a strong technical know-how to deliver hign-impact mdoenisaton projects;
• Minimum 8 years of design and implementation experience in Enterprise Architecture Governance, Solution Architect, Distributed Applications, and Service Oriented Architectures ( SOA ) Frameworks;
• Experience in designing, developing and deploying large, scalable production applications on Cloud / PaaS platforms and Containers (such as AWS, Google and Azure);
• Experience in modern full-stack web application technologies; experience in modern front-end engineering like Next.Js/React.js and Java/TypeScript on the backend;
• Experience in overall governance of IT solutions, framework, policies, processes, and rules that ensure effective, consistent, and compliant execution of technology solutions;
• Proficient in conceptualizing and deriving common architectural designs across multiple services;
• Highly conversant in architectural concepts, principles and SOA governance practice;
• Solid Agile development experience and has experience architecting large enterprise-wide systems;
• Strong stakeholder management skills with the ability to communicate architecture methods, concepts, standards and policies;
• Customer-centric individual, possess strong leadership and interpersonal skills;
• Excellent communication and interpersonal skills, and able to work well with cross-organizational teams.

Desired Skill-set

• Certified in TOGAF / ITIL / COBIT.

Responsibilities

• Advise and lead project team’s engineering vision, strategy, and directions that align with the organization’s overall vision and goals;
• Conceptualize, Architect, Design Digital Solutions & Research on current state, identify the gaps and map out the to-be state and roadmap for both greenfield and brownfield implementations;
• As a lead architect - establish a long-term technical plan and roadmap for the project teams;
• Ensure regular administration of architecture review including facilitation of resolution of feedback, tracking and follow up for effective closure of design gap;
• Provide direction and guidance to team members in establishing architecture policies, standards, processes and platform to drive scalability and proposed changes where required;
• Partner with cross-functional teams to develop quality, reliability, and security strategies solutions;
• Guide application operations, propose new solution methodologies and mentor the team raising the collective technical competencies;
• Ensure collaboration to maintain up-to-date architecture and solution artefacts as well as communication materials for stakeholders, technology forums, and community engagements.

Should you be interested in this career opportunity, please send in your updated resume to apply@sciente.com at the earliest.

When you apply, you voluntarily consent to the disclosure, collection and use of your personal data for employment/recruitment and related purposes in accordance with the SCIENTE Group Privacy Policy, a copy of which is published at SCIENTE’s website (https://www.sciente.com/privacy-policy).

Confidentiality is assured, and only shortlisted candidates will be notified for interviews.

EA Licence No. 07C5639

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.

Product area

At Google we work hard to earn our users’ trust every day. Trust & Safety is Google’s team of abuse fighting and user trust experts working daily to make the internet a safer place. We partner with teams across Google to deliver bold solutions in abuse areas such as malware, spam and account hijacking. A team of Analysts, Policy Specialists, Engineers, and Program Managers, we work to reduce risk and fight abuse across all of Google’s products, protecting our users, advertisers, and publishers across the globe in over 40 languages.

Job description

Trust & Safety team members are tasked with identifying and taking on the biggest problems that challenge the safety and integrity of our products. They use technical know-how, excellent problem-solving skills, user insights, and proactive communication to protect users and our partners from abuse across Google products like Search, Maps, Gmail, and Google Ads. On this team, you're a big-picture thinker and strategic team-player with a passion for doing what’s right. You work globally and cross-functionally with Google engineers and product managers to identify and fight abuse and fraud cases at Google speed - with urgency. And you take pride in knowing that every day you are working hard to promote trust in Google and ensuring the highest levels of user safety.

Additional job description

As a Workspace Trust and Safety Engineering Analyst, you will develop insights on abuse trends and establish a foundation for managing various Trust and Safety escalations across Workspace. This role is crucial in streamlining related processes and ensuring a safer Workspace experience for all users (both consumers and Workspace enterprises). You will be a partner to bring together teams to address the most critical abuse problems impacting our users. You will identify, quantify, and help address the problems and work across Google and the broader industry.

Qualifications

Job responsibilities

• Extract, transform, and analyze Google Workspace log data using advanced analytical methods to solve abuse challenges, investigate escalations to uncover vulnerabilities and tactics used by bad actors.
• Lead comprehensive analyses to deliver insights on abuse trends, directly contributing to the design and improvement of anti-abuse product protections.
• Partner with Engineering, Product Managers (PMs), Program Managers (PgMs), Data Scientists, and external groups to qualify, quantify, and understand complex abuse challenges while co-developing company-wide counter-abuse strategies and improvements.
• Establish foundational frameworks to streamline Workspace Trust and Safety escalations, and quantify the impact of anti-abuse teams to build internal and external awareness of best practices.

Minimum qualifications

• Bachelor's degree or equivalent practical experience.
• 2 years of experience in data analysis, including identifying trends, generating summary statistics, and drawing insights from quantitative and qualitative data.
• 2 years of experience managing projects and defining project scope, goals, and deliverables.
• 2 years of experience in manipulating data sets using SQL or other programming or scripting languages.

Preferred qualifications

• Master's degree in a quantitative discipline.
• 2 years of experience with one or more of the following languages: SQL, R, Python, or C++.
• 2 years of experience with machine learning systems.
• Excellent written and verbal communication skills.
• Excellent problem-solving and critical thinking skills with attention to detail in an ever-changing environment.

Why Join
Protecting our customers' assets and data is at the heart of everything we do at OCBC. As a Cyber Engineering - Risk professional, you'll play a critical role in safeguarding our systems and networks from cyber threats. You'll be part of a team that's shaping the future of cybersecurity in the financial industry.

How you succeed

We are seeking an experienced cybersecurity engineering leader to lead the Cyber Technology Support (CTS) function and drive its evolution towards a scalable, engineering‑driven and intelligence‑led operating model.

This position requires a strategic thinker with strong hands‑on engineering background, deep familiarity with enterprise‑grade cybersecurity ecosystems, and proven experience in cybersecurity transformation. The successful candidate will play a critical role in transforming CTS into a modern cyber engineering capability—focused on service reliability, service quality, and process automation—while working closely with Security Operations, Architecture, Risk, and Infrastructure teams to enhance overall cyber defense effectiveness.

What you do

Lead a team of approximately 10–15 engineers responsible for the delivery, operation, and continuous uplift of enterprise cybersecurity platforms across network, endpoint, SIEM, cloud, and data security domains.

Stabilise operations and drive consistency across incident, problem, and change management processes.

Establish clear accountability, ownership models, and escalation paths.

Lead CTS engagement in solution evaluation, design review, testing, and onboarding of new cybersecurity capabilities.

Continuously uplift engineering practices, documentation, and runbooks.

Lead CTS to transition into intelligence-led and engineering-driven platform capabilities

Ensure CTS services are aligned with regulatory requirements (e.g., MAS TRM) and internal policy expectations.

Support audit preparation through consistent controls, evidence readiness, and operational transparency.

Contributes to development and reporting of KRIs, service metrics, and control effectiveness indicators for senior management.

Who you are

15+ years of experience in cybersecurity, preferably within banking, financial services, or large regulated enterprises.

Proven experience leading cybersecurity engineering, cyber defense, or security platform teams at scale.

Strong background across enterprise security domains such as SIEM, endpoint, network, cloud, and data security platforms.

Demonstrated experience driving automation, orchestration, and operational uplift.

Familiarity with detection engineering, threat-driven security, or intelligence-led operating models is highly preferred.

Strong understanding of regulatory, audit, and compliance environments (e.g., MAS, HKMA).

Proven ability to balance operational stability with transformation and modernisation initiatives.

Strong leadership presence with excellent stakeholder management and cross-functional collaboration skills.

Ability to operate effectively in complex, matrixed environments with evolving priorities

Who we are
As Singapore's longest established bank, we have been dedicated to enabling individuals and businesses to achieve their aspirations since 1932. How? By taking the time to truly understand people. From there, we provide support, services, solutions, and career paths that meet their individual needs and desires.

Today, we're on a journey of transformation. Leveraging technology and creativity to become a future-ready learning organisation.
But for all that change, our strategic ambition is consistently clear and bold, which is to be Asia's leading financial services partner for a sustainable future.

We invite you to build the bank of the future. Innovate the way we deliver financial services. Work in friendly, supportive teams. Build lasting value in your community. Help people grow their assets, business, and investments. Take your learning as far as you can. Or simply enjoy a vibrant, future-ready career. Your Opportunity Starts Here.

Step into a career with ASM, where cutting edge technology meets collaborative culture. ​

For over 55 years ASM has been ahead of what’s next, at the forefront of innovation and what’s technologically possible. With more than 4,500 ASMers representing 70 nationalities, our people and our advanced semiconductor devices are playing a crucial role in trends such as 5G, cloud computing, AI, and autonomous driving.  But we’re more than just a tech company. We value diversity, inclusion and sustainability as we strive to make a positive impact on the world.  Our development programs help support your growth, shaping your future and pushing the boundaries of innovation to unleash potential.  

Job's mission

As a Principal Engineer, Electrical Engineering at ASM, you will act as a technical lead for electrical systems within advanced semiconductor equipment. You will drive system-level design decisions, ensuring robust architecture, seamless integration, and high-performance delivery. By combining deep technical expertise with strong ownership, you will guide the development of complex systems from concept through production while influencing cross-functional engineering outcomes.

What you will be working on

• Lead the design and development of electrical systems and sub-assemblies, setting technical direction and ensuring alignment with product architecture
• Lead fabrication and test of electrical test structures (ex. MOS capacitors, MIM capacitors, FETs) for semiconductor logic and memory applications
• Own system-level integration, ensuring electrical, mechanical, and control elements work cohesively to meet performance, safety, and reliability targets
• Define and validate digital and5 analog I/O architectures, enabling flexible, customer-specific configurations
• Drive technical decision-making across new product development, capital projects, and system improvements
• Review and approve engineering changes, ensuring technical integrity, risk mitigation, and adherence to timelines
• Act as a key contributor in design reviews, providing expert guidance and ensuring readiness for production release
• Define and oversee system validation strategies, including hardware testing, instrumentation, and performance verification
• Analyze, understand and interpret electrical test data (ex. CV, IV, Dit) to guide process development and integration of ASM's products such as ALD films
• Evaluate feasibility of new concepts and technologies, solving complex system-level challenges with a structured and innovative approach
• Influence and collaborate with global cross-functional teams, acting as the electrical domain expert
• Mentor and guide junior engineers, elevating technical capability within the team
• Drive high-quality technical documentation, reporting standards, and stakeholder alignment

What we are looking for

• Master’s or PhD in Electrical and Electronics Engineering
• Minimum 5 years of experience in system engineering within semiconductor equipment manufacturing
• Strong expertise in electrical hardware design, system architecture, and integration (e.g., reactors, plasma sources, or similar systems)
• Proven ability to lead technical problem-solving and make system-level design decisions
• Proficiency in AutoCAD and data analysis tools such as JMP
• Hands-on experience in hardware testing, instrumentation, and system validation
• Ability to operate effectively in a fast-paced, global engineering environment
• Strong communication skills in English, with the ability to influence technical discussions

What sets you apart

• Experience acting as a technical lead or subject matter expert on complex engineering projects
• Strong understanding of semiconductor processes and equipment architecture
• Experience defining or improving system validation strategies and test methodologies
• Familiarity with data analysis or scripting tools (e.g., Python)
• Proven track record of driving cost reduction, reliability improvements, or product innovation
• Experience working across regions or with international engineering teams
• Proactive, ownership-driven mindset with the ability to influence without formal authority

Apply today to be part of what’s next.

We make the tech that enables the chips in devices which improve lives around the world. We do this with an eye to the future, pushing the boundaries of what’s possible through cutting-edge innovation, and driving the next wave of technological breakthroughs that shape how we live, work, and connect.

To learn more about ASM, find us at asm.com and on LinkedIn, Facebook, Instagram, X and YouTube.

ASM is an equal opportunity employer and considers qualified applicants for employment without regard to race, color, religion, age, nationality, social or ethnic origin, sexual orientation, gender, gender identify or expression, marital status, pregnancy, political affiliation, disability, genetic information, veteran status, or any other characteristic protected by law.

• MNC Company
• Basic $2200 - $2500 + AWS + Variable Bonus
• Excellent Welfare and Benefits + Career progression
• Working location: West
• Working hours: Monday to Friday (8.30am to 5.30pm)

Job Responsibilities:

• Responding to calls for scheduled and unscheduled maintenance service request in accordance with the Company’s Service Agreement
• To trouble-shoot and repair any system abnormality during maintenance service call at the customers’ premises
• To supervise and control sub-contractors’ work quality for maintenance work and to render technical support to the other departments’ staff
• Any others ad hoc duties as assigned

Job Requirements:

• Possess minimum Nitec in Electronics and/or Electrical Engineering or relevant
• Possess minimum 1 year of experience in service and maintenance of alarm, card access and CCTV systems

Candidates are encouraged to apply this position via Apply Now button with the following information in the resume

• Work experiences and job responsibilities
• Current and Expected salary
• Reason for leaving
• Date of availability
• Education background

We regret that only shortlisted candidates will be contacted.

LIONG ZHAO GUAN (R22107632)

EA Recruitment Pte Ltd

EA License No: 21C0492