Total 12 Senior Executive operations advisor job vacancies in Manufacturing / Production category in Singapore

As Frontend Central Product Integration Engineering and transformative (CPIE) team at Micron Technology, Inc., you will be leading new initiatives to deliver pioneering process capability, best-in-class bits per wafer (Yield) with the highest quality and fastest speed through innovation and collaboration with multi-functional teams. Your primary focuses include but not limited to:

Initiate new data solutions and methodologies to:

• identify process, test, and design improvement opportunities, specialized in UE_ROW & all quality index, Front End-PTS integration, and high-value-bits (PG2+) yield;

• modeling, monitoring and aiming for tool performance benchmarking;

• Process equipment prognostics and process integration optimization;

• Identity test optimization opportunities for high product grade yield improvement.

• Collaborate with site Process & Equipment Engineering, Manufacturing(MFG), Product Integration Engineering (PIE) and Data Science (DS) team to establish feasibility of new initiatives, demonstrate business values, and prototype solution mock-ups;

• Partner with Global Quality (GQ), Product Engineering (PE), Central PEE(CPEE), Smart Mfg Artificial Intelligent (SMAI), Technology Development (TD), and Suppliers to deliver end to end solutions, implement BKM development and deployment to production.

• Integrates AI-assisted tools and insights into daily work to improve efficiency, quality, or effectiveness,exercising sound judgment and complying with organizational standards and legal requirements.

• Contributes to a culture of continuous improvement by identifying, testing, and sharing AI-enabledenhancements within one’s scope of work.

Collaboration

• Partner closely with multi-functional teams to ensure successful communication and collaboration for project implementation.

• Detail oriented with the ability to work independently

• Dependability and able to work effectively in multi-functional teams.

• Facilitate and lead activities in designing and optimizing current system, methods, tool, skill to be Best In industry.

• Manage priorities and enhancements to improve business processes and existing systems that are global in nature.

• Willing to work during non-standard hours when needed to provide support to engineering teams at any Micron site.

• Strong growth mindset and willing to continue to learn, unlearn, relearn.

Communication

• Effective communication skills in verbal/written.

• Self-motivated. Able to work independently with minimal supervision.

• Able to travel as required to support department and company objectives.

Requirement and Technical Competency:

• Experience in PIE, Test solution team, product engineering and circuit design engineering. Understanding of Process/Product Integration will be advantageous;

• In depth knowledge of processes, equipment and control system;

• Proficiency in data analytical tools such as Y3, JMP, Python to perform numerical experiment. Proficiency in Statistical/Machine Learning will be additional advantageous; 

• Proven track record to make decisions, multi-task, and solve problems and address root causes.

• Exhibit critical thinking to find opportunities.

• PhD/Masters/Bachelors with relevant course of study and experience

• Ability to apply baseline digital fluency and role‑appropriate AI literacy to use AI‑enabled tools responsibly and effectively for research, analysis, content creation, problem‑solving, operational tasks, and achieving business outcomes.

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.
  

  Performs hardware, software, semiconductor design or telecomm engineering assignments. This job mapping should be used only if the position cannot be mapped specifically to other design/development engineering jobs.

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Experience Level & Entry Consideration

This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.

• Fresh Bachelor’s/Master’s / PhD Graduates

• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.

• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.

• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.

• Experienced Engineers (Eligible for Higher GJS)

• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.

• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.

• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making.

Required Qualifications

• Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.

• Strong fundamentals in semiconductor devices, wafer test, and product engineering.

• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.

• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.

• Strong analytical skills and ability to drive structured root‑cause analysis.

• Effective communication skills and ability to work across global, cross‑functional teams.

Preferred Qualifications

• Experience with NAND / memory products.

• Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues.

• Exposure to probe flow optimization, yield learning, or test cost reduction.

• Familiarity with DFT verification, reliability screening, or test correlation methodologies.

• Experience with Python, SQL, JMP, or data / ML tools.

• Demonstrated ability to independently drive complex technical problems from concept through execution.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.

• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.

• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.

As a key leader within High Bandwidth Memory (HBM) Product Engineering Media Health team, you will spearhead and develop a high performing team driving both intrinsic and extrinsic reliability test development and execution for Micron’s latest HBM products, both on DRAM and Interface die and a stacked product. Your responsibility is to drive extrinsic DPM reduction (Time 0 and Field DPM) and lead the intrinsic reliability charter, along with optimized Manufacturing Test Flow to meet critical KPI’s Quality, Cost and Cycle Time. You will be leading the team to characterize the products from reliability aspect, identify the reliability gaps, working on root cause and resolution of qual and RMA failures pertaining to defectivity and intrinsic reliability margin and drive fab process improvement driven by the qual failures. Additionally, your team will also be the key person in frontend process conversion, where you will work with Fab, TD, GQ teams to establish robust business process for process conversions to facilitate yield improvements, DPM and Cost Reduction. You will collaborate across functions within and outside of HBM to meet both strategic and tactical objectives while continually maximizing the effectiveness of the HIG HBM PE organization. The future of HBM are exciting and dynamics. Micron is seeking experienced individuals that find technical challenges engaging and invigorating.

Responsibilities:

• Reliability Test Flow Development: Define and develop reliability stress, test flows and test plans to cover all Product Reliability aspects.

• Reliability Test Plan and Execution: Work closely with Global Quality team to define qualification plan, review and manage the qualification execution progress, and drive for qualification gating issue resolution.

• DPM reduction: Drive down and achieving Extrinsic Reliability (Time 0 and Field DPM) and Intrinsic Reliability through Optimized Manufacturing Test Flows and Test Strategy to meet critical KPI’s Quality, Cost and Cycle Time

• Root Cause and Resolution of Qual and RMA Device Issues pertaining to defectivity and intrinsic reliability: Debug and identify root cause and failures in reliability tests by electric failure analysis(EFA) and Physical Failure Analysis (PFA) and drive for resolution and improvements through cross functional team collaboration.

• Process Conversions and HVM: The role involves providing recommendation to fab teams for new process conversions to reduce cost, increase yields. This is critical as it directly impacts the yield, quality, reliability, and performance of HBM products, which are key components in many modern technologies.

• Risk Management: The role requires communication with Product Managers/Leads to manage risks associated with DPM process conversions. This is crucial in ensuring that the conversions move at an appropriate pace, balancing the need for innovation with the need for stability and reliability.

• Promotion of Innovation: The role involves promoting innovation and driving for changes that will provide Micron with a technical advantage over its competition. This is vital for maintaining Micron’s competitive edge in the market.

• Mentorship and Development of Others: The role involves actively developing and mentoring others. This is important for the growth and development of the team and the organization.

• Project Management: Developing project management skills within the team ensures efficient execution of projects, leading to timely delivery of technological solutions.

• Technical Decision Making: The role involves making final decisions on risk analysis and project prioritization. These decisions directly impact the direction of technological development.

• Cross-Functional Collaboration: This role necessitates collaboration with various cross-functional teams such as Fab, HBM Technology Development, HBM Design, System Development, and Quality/Reliability team. This collaboration is vital for the holistic development and shipping of end products.

Requirements

• Bachelors/Masters Electrical and Electronics Engineering Degree with 3 years of experience in the semiconductor industry. Product Engineering experience is preferred.

• Demonstrating Strong Leadership Skills and Technical Skills, especially in problem solving with root cause understanding and solution space through in depth circuit analysis.

• Good knowledge of statistics and data analysis tools and scripting.

• Dedicated and highly motivated with a flexible approach towards adapting to different roles in a dynamic working environment (from leading the team to leading technical programs).

• Proven track record of collaborative work within/across teams to address sophisticated business and engineering problems.

• Strong sense of responsibility and accountability towards assigned role with professional work ethic.

• Excellent communication and presentation skills.

• Passionate about people leadership, with a drive toward ongoing learning and development in this area.

• Work on site in Singapore with international travel to US, Taiwan and Japan.

Our vision is to transform how the world uses information to enrich life for all.  
 
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. 

As part of the HIG HBM Product Engineering organization, you will help drive the development of next-generation GenAI, machine learning, and advanced data analytics solutions for semiconductor engineering. In this role, you will work on intelligent systems that improve engineering productivity, strengthen technical decision-making, and unlock insights from complex manufacturing, validation, and engineering workflows. 

You will collaborate with cross-functional teams across Product Engineering, Design Engineering, System Engineering, Data Science, IT, and Manufacturing to prototype, build, and scale practical AI-driven solutions that improve quality, cost, cycle time, and engineering efficiency. 

Key Responsibilities 

• GenAI System Development: Design, build, and improve GenAI-powered and agentic systems supporting semiconductor engineering workflows such as code generation, data extraction, analytics, documentation automation, failure triage, and technical knowledge retrieval.  

• Large-Scale Data Pipelines: Develop scalable data pipelines and analytical workflows to ingest, clean, transform, and analyze large, complex, and heterogeneous datasets from multiple manufacturing and engineering systems.  

• Advanced Data Analytics: Apply Python, SQL, and data science libraries (e.g., pandas, matplotlib) to perform deep analysis, generate visualizations, and deliver actionable engineering insights.  

• LLM Workflow Engineering: Build, evaluate, and optimize LLM-based workflows, including prompting, retrieval-augmented generation (RAG), inference orchestration, benchmarking, and quality evaluation.  

• Machine Learning Production: Develop and productionize machine learning and deep learning models for classification, regression, anomaly detection, failure analysis, and engineering decision support.  

• Distributed Data Processing: Implement robust data processing techniques such as data cleansing, outlier detection, and missing-data handling using distributed or large-scale frameworks (e.g., PySpark, BigQuery).  

• Cross-Functional Collaboration: Partner with domain experts and cross-functional teams to translate complex engineering problems into scalable AI/ML and analytics solutions.  

• Production Deployment: Support deployment, monitoring, and operationalization of AI/ML solutions in cloud and enterprise environments.  

• Technical Communication: Communicate technical findings, recommendations, and model outcomes clearly to both technical and non-technical stakeholders.  

• Innovation Leadership: Identify and drive high-impact opportunities where GenAI, machine learning, and analytics can improve engineering productivity and business outcomes. 

Minimum Qualifications 

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, Data Science, Statistics, Artificial Intelligence, or a related field. 

• Minimum 2 years of hands-on experience developing and deploying AI applications in semiconductors, electronics, or other engineering industries. 

• Strong programming proficiency in Python and SQL.  

• Strong technical foundation in data analytics and visualization, including tools and libraries such as pandas, scikit-learn, matplotlib, plotly, or similar ecosystems.  

• Familiarity with agentic AI frameworks such as LangGraph, Google ADK, AutoGen and evaluation tools like AgentEval. 

• Familiarity with modern AI coding tools / agentic coding harnesses, such as Claude Code, Roo Code, Cursor, Cline, Windsurf, Gemini CLI, or similar tools.  

• Hands-on experience developing and deploying AI/ML systems involving LLMs, including RAG, agentic workflows, and frameworks such as PyTorch or TensorFlow. 

• Cloud experience with GCP, AWS, or Azure, including deploying ML pipelines in production. 

• Experience with LLM training, inference, and evaluation workflows, including prompt design, benchmarking, validation, or retrieval-augmented systems.  

• Experience analyzing large, complex, and heterogeneous datasets from multiple systems and applying sound techniques for data cleansing, outlier handling, and missing-data treatment.  

• Strong analytical, problem-solving, and software development skills.  

• Strong communication skills with the ability to explain technical concepts and findings effectively.  

• Strong sense of ownership, accountability, and engineering rigor. 

Preferred Qualifications 

• Experience building agentic systems or AI solutions for semiconductor manufacturing, product engineering, validation, yield improvement, reliability, or failure analysis. 

• Deep understanding of semiconductor-specific AI/ML applications 

• Demonstrated understanding of deep learning architectures and computer vision.  

• Experience using enterprise data platforms such as BigQuery, Snowflake, MSSQL, Oracle, or Redshift. 

• Experience with Kubernetes or similar production infrastructure and deployment frameworks. 

• Experience with web application technologies such as JavaScript, HTML, and CSS.  

• Experience designing scalable, enterprise-grade AI/ML systems with attention to reliability, traceability, and operational readiness. 

• Familiarity with document-processing pipelines, technical knowledge platforms, or retrieval systems for engineering content. 

• Experience working in cross-functional environments spanning engineering, manufacturing, data science, and IT. 

As a senior individual contributor in System and Technology Product Group (STPG), you will provide technical leadership across the full learning loop of a test chip vehicle (TCV) - shaping pre-silicon simulation and regression strategy before tape-out, driving silicon debug after bring-up, and converting data into durable design, model, and methodology improvements for next-generation NAND flash memory products. This role is expected to independently identify risk, define solutions, and influence cross-functional technical direction.

Key Responsibilities

Pre-Silicon Simulation, Coverage & Regression Ownership

• Own pre-silicon‑ validation strategy for TCV, partnering with Design, Process, and TD to define what must be proven in simulation versus silicon.

• Develop, maintain, and execute robust simulation and regression frameworks (functional, parametric, stress, and corner) aligned to TCV objectives.

• Define coverage expectations and exit criteria for pre-silicon regressions, identifying‑ gaps and latent risks early.

• Analyze simulation results to surface architecture, device, and margin sensitivities, driving design updates and tape‑out readiness decisions.

• Establish and enforce simulation ↔ silicon correlation methodology to ensure modeling fidelity and learning continuity.

TCV Definition, Bring-Up & Silicon Validation

• Provide technical ownership for TCV bring-up from first silicon through full characterization readiness.

• Define probe enablement, trims, operating conditions, and debug strategies to accelerate stable and informative silicon access.

• Lead execution of electrical characterization plans validating array, periphery and experimental features against design and process intent.

• Drive deep root cause analysis for silicon anomalies, distinguishing design, process, model, or test limitations.

Test Content & Methodology Leadership

• Architect TCV specific test modes, patterns, and flows to maximize learning efficiency and data quality.

• Partner with Test Solutions Engineering (TSE) to influence probe architecture and infrastructure supporting TCV for protocol evolution.

• Define voltage, timing, and temperature stress strategies to expose true design and process limits beyond nominal behavior.

Cross-Functional Technical Leadership & Influence

• Serve as a go-to technical expert across Design, TD, Process and Test for TCV and early silicon topics.

• Translate simulation and silicon findings into clear, actionable recommendations that influence design fixes, model updates, and next generation architectures.

• Lead complex debug efforts with ambiguous data, setting technical direction by crystalizing multifaceted information.

• Role-model technical leadership through active mentoring and talent development to support Micron’s long-term success.

Data Analysis, Correlation & Knowledge Capture

• Spearhead AI adoption to perform advanced data analytics across large simulation and silicon datasets.

• Author high-impact technical documentation capturing learnings, best practices, and reusable methodologies for STPG and broader org consumption.

Requirements:

• Bachelor’s or post-graduate degree in Electrical/ Electronics/ Computer Engineering or related field, with minimum 5 years of relevant industrial experience.

• Strong fundamentals in CMOS/ MOSFET device physics, memory circuits, and semiconductor devices.

• Demonstrated experience owning pre-silicon simulation/regression and post-silicon test/ validation for complex designs.

• Strong capability in data analysis and scripting (Python, JMP, or equivalent) applied to large datasets.

• Proven ability to drive ambiguous technical problems to closure with minimal supervision.

• Deep experience with NAND Flash architectures, array/periphery interactions, and test chips is preferred.

• Working knowledge of DFT, probe test infrastructure, and failure analysis.

• Experience with firmware-assisted‑ test modes and experimental silicon features.

• Exposure to automation, ML/AI, or advanced analytics applied to simulation and silicon learning loops.

• Candidates may be considered for higher job grades if they exceed 10 years of relevant experience.

Key Responsibilities

• Lead and drive global Product Integration initiatives to improve yield, quality, and benchmark performance across technology nodes and products.

• Centralize and synthesize project information (design requirements, test challenges, yield learning) from multiple global teams and drive execution to closure.

• Drive yield breakthroughs by understanding the end‑to‑end test flow, product design and operation, packaging interactions, and manufacturing processes while balancing yield vs. reliability requirements.

• Foster technical innovation by characterizing device failure modes using deep knowledge of device architecture, physics, packaging interaction, and available test/process knobs.

• Define and drive strategies to ensure Packaging Technology and Chip‑Package Interaction are developed and qualified ahead of product qualification.

• Lead cross‑functional and cross‑site taskforces (Product, Test, Yield, Design, Fab, Packaging, Quality, TD) to resolve yield and quality challenges in a timely manner.

• Promote network Best‑Known‑Method (BKM) development, standardization, and business process creation or re‑engineering to improve productivity and efficiency.

• Maintain strong working relationships with stakeholders in Fab, Technology Development, Product Engineering, Test Engineering, Quality, and Packaging teams.

• Communicate project status, risks, and proposals effectively through clear written reports and technical presentations.

• Proactively identify obstacles, escalate when needed, and partner with management to drive successful outcomes.

• Travel to Micron fab and development sites as needed to support project execution and alignment.
  

  Minimum Qualifications

  • Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Microelectronics, Physics, Chemistry, Materials Science Engineering, or a related field.

  • 2+ years of experience in one or more of the following:

  • Product Integration

  • Test Engineering

  • Yield Engineering

  • Design Engineering

  • BEOL semiconductor processing or process integration

  • Strong knowledge of Semiconductor Device Physics and DRAM product operations.

  • Understanding of wafer fabrication process flows, parametric/electrical testing, and probe yield.

  • Strong data analysis, debugging, troubleshooting, and problem‑solving skills with attention to detail.

  • Effective verbal and written communication skills with the ability to present to both small and large technical audiences.

  • Demonstrated ability to collaborate across functions and cultures, building strong customer and co‑worker relationships.

  • Ability to work independently with minimal supervision, manage multiple priorities, and stay organized.

  • Intermediate to advanced PC skills, including Microsoft Office.

  • Willingness to travel approximately 20–50% to support global project needs.

  • Flexibility to adapt to changing priorities and take on additional responsibilities as needed.

  Preferred Qualifications

  • Experience in DRAM High Bandwidth Memory (HBM) products.

  • Exposure to DRAM HPM, advanced packaging, chip‑package interaction, BEOL integration, or layout‑related topics.

  • Experience working across Test, Product, Yield, Design, Packaging, and Manufacturing organizations.

  • Proven ability to drive alignment and execution in central or network‑level roles.

  • Strong interest in innovation, continuous improvement, and scalable solution development.

As Front End Central Product Integration Engineer-Chip Package Interaction at Micron Technology, Inc., you will be responsible for working with global Micron network to drive each silicon node's Packaging Product yield, quality improvement, new product introduction (NPI) through technical expertise, business process management and project execution.

In addition, you will be responsible in integrating solutions by connecting cross-functional expertise, standardizing the business process and regularly benchmarking internal and external intelligence to achieve the highest value bits and productivity. 

Responsibilities and Tasks

• Promote worldwide synergy for improved benchmark performance and efficiency gains through global project management and execution, network BKM leveraging and enhancement, and business process creation and re-engineering.

• Define strategies to ensure that Packaging Technology and interaction with Front End manufacturing process are fully developed and qualified well ahead of any qualification of the product itself.  

• Lead the PI Loop taskforce and/or team in network to address yield and quality challenges, optimize process flow in a timely manner to achieve BIC yield performance.

• Maintain and enhance domain knowledge and technical expertise, explore innovation opportunities with strategic thinking and systematic approach.

• Maintain a strong and open relationship with peer group and managers in other functional areas within central team and outside in areas such as Fab, TD, Product Engineering, GQ. Communicate and respond to issues in a timely manner. Help drive to fix the issue where necessary.

• Demonstrate ability to give effective presentations to both small and large groups on project updates and new initiative proposals.

• Periodically follow up with manager to ensure all type of goals are met and get assistance to remove obstacles.

• Travel to Micron Fab locations as necessary for face-to-face work.

Requirements

• Bachelor’s  or Master's degree in Electrical Engineering, Microelectronics, Physics, Chemistry, Material Science Engineering or related field

• A minimum of 2 years of experience in Back-End-of-Line (BEOL) semiconductor processing or process integration is required

• Must be willing to travel as needed to support departmental goals, with an expected travel frequency of approximately 20–50%

• Knowledge in Semiconductor Device Physics, DRAM operations, wafer fabrication process flows, parametric/electrical test and probe yield.

• The experience on DRAM HPM, BEOL integration, advanced packaging and layout will be a plus to this job position.

• Good data analysis, troubleshoot, problem solving, reporting and presentation skills with a strong attention to detail.

• Good multi-tasking, verbal, and written communication skills.

• Strong interpersonal skills and customer/co-worker relationships. Successfully demonstrated teamwork skills with a strong focus on developing good team dynamics.

• Good organizational capabilities and ability to work effectively with minimal supervision.

• Intermediate to advanced PC skills including Microsoft Office.

• Ability to be flexible with job responsibilities and take the initiative to assume added responsibilities.
  

  Maximizes yield by working on tools, the process, or wafer fabrication recipes. Troubleshoots wafer fabrication problems and performs root cause analysis. Works with other process areas to understand and control process deviations. Long-term investigation of defect issues may require extensive work with shift engineering and other functional areas. Evaluates products to ensure they meet the required design and performance specifications. Conducts research to assess process adjustment requirements and recommends process improvements or equipment changes needed to efficiently manufacture new product or part types.

Responsibilities and Tasks:

• Drive end‑to‑end front‑end process integration across multiple modules to support yield, functionality, and scalability

• Lead cross‑module root cause analysis for complex yield detractors and integration issues

• Support yield ramp, derivative matching, and node transitions through focused integration execution

• Act as a core cPIE contributor for assigned programs, partnering closely with site PI/PE/Device teams

• Develop and apply Best Known Methods (BKM) within owned integration scope

• Provide technical input to POR/TOR and ECN decisions affecting integration margin

• Apply data‑driven analysis to quantify process sensitivity, margin, and risk

• Participate in SWAT teams and technical deep dives for high‑impact issues

• Mentor junior engineers and contribute to knowledge sharing within CPIE

• Collaborate with PI, PE, Device, Yield, TD, and Quality to accelerate learning cycles

Required Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Chemical Engineering, Physics, or a related discipline

• At least 3 years of strong front‑end semiconductor manufacturing experience, with demonstrated exposure to process integration across multiple modules

• Proven ability to perform complex root‑cause analysis on yield, functionality, or integration issues using data‑driven methods

• Solid understanding of device–process interactions and system‑level integration trade‑offs

• Experience collaborating across PI, PE, Device, Yield, TD, and Quality organisations

• Ability to influence technical decisions through analysis, insight, and technical credibility

• Strong written and verbal communication skills for technical reviews, deep dives, and cross‑team alignment

Good to Have:

• Direct experience supporting advanced DRAM technology nodes and/or technology ramps

• Demonstrated ownership of integration loops, yield ramp activities, or derivative matching efforts

• Experience contributing to or developing Best Known Methods (BKM), standard practices, or reusable integration solutions

• Familiarity with POR/TOR definition, ECN review, and change risk assessment from an integration perspective

• Exposure to statistical analysis, yield modelling, or advanced analytics applied to manufacturing data

• Track record of leading or contributing to SWAT teams or high‑impact technical investigations

• Experience mentoring junior engineers or serving as a technical reference within a team
  

  Maximizes yield by working on tools, the process, or wafer fabrication recipes. Troubleshoots wafer fabrication problems and performs root cause analysis. Works with other process areas to understand and control process deviations. Long-term investigation of defect issues may require extensive work with shift engineering and other functional areas. Evaluates products to ensure they meet the required design and performance specifications. Conducts research to assess process adjustment requirements and recommends process improvements or equipment changes needed to efficiently manufacture new product or part types.

Responsibilities and Tasks:

• Drive end‑to‑end front‑end process integration across multiple modules to support yield, functionality, and scalability

• Lead cross‑module root cause analysis for complex yield detractors and integration issues

• Support yield ramp, derivative matching, and node transitions through focused integration execution

• Act as a core cPIE contributor for assigned programs, partnering closely with site PI/PE/Device teams

• Develop and apply Best Known Methods (BKM) within owned integration scope

• Provide technical input to POR/TOR and ECN decisions affecting integration margin

• Apply data‑driven analysis to quantify process sensitivity, margin, and risk

• Participate in SWAT teams and technical deep dives for high‑impact issues

• Mentor junior engineers and contribute to knowledge sharing within CPIE

• Collaborate with PI, PE, Device, Yield, TD, and Quality to accelerate learning cycles

Required Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Chemical Engineering, Physics, or a related discipline

• At least 3 years of strong front‑end semiconductor manufacturing experience, with demonstrated exposure to process integration across multiple modules

• Proven ability to perform complex root‑cause analysis on yield, functionality, or integration issues using data‑driven methods

• Solid understanding of device–process interactions and system‑level integration trade‑offs

• Experience collaborating across PI, PE, Device, Yield, TD, and Quality organisations

• Ability to influence technical decisions through analysis, insight, and technical credibility

• Strong written and verbal communication skills for technical reviews, deep dives, and cross‑team alignment
  

  Good to Have:

  • Direct experience supporting advanced DRAM technology nodes and/or technology ramps

  • Demonstrated ownership of integration loops, yield ramp activities, or derivative matching efforts

  • Experience contributing to or developing Best Known Methods (BKM), standard practices, or reusable integration solutions

  • Familiarity with POR/TOR definition, ECN review, and change risk assessment from an integration perspective

  • Exposure to statistical analysis, yield modelling, or advanced analytics applied to manufacturing data

  • Track record of leading or contributing to SWAT teams or high‑impact technical investigations

  • Experience mentoring junior engineers or serving as a technical reference within a team
    

    Maximizes yield by working on tools, the process, or wafer fabrication recipes. Troubleshoots wafer fabrication problems and performs root cause analysis. Works with other process areas to understand and control process deviations. Long-term investigation of defect issues may require extensive work with shift engineering and other functional areas. Evaluates products to ensure they meet the required design and performance specifications. Conducts research to assess process adjustment requirements and recommends process improvements or equipment changes needed to efficiently manufacture new product or part types.