Total 257 technology development job vacancies in Engineering category in Singapore

Key Responsibilities

• Lead, mentor and deliver technical contributions for designing advanced high bandwidth ASIC packages.
• Conduct advanced power and signal integrity analysis for board and MCM packages.
• Provide expert design guidance for power distribution networks, collaborating with digital design, package, and board teams.
• Recommend and implement improvements to power and signal nets, enhancing overall system reliability.
• Perform circuit simulations using Hspice netlists and full-chip models.
• Develop and validate behavioral models (IBIS) for I/Os, supporting high-speed USB3/USB2 interfaces in integrated mobile platforms.
• Utilize industry-standard tools (Cadence PowerSI, 3DEFM, T2B, PowerDC, Agilent ADS, Nimbic, AllegroSIP) for analysis and design.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or related field.
• Familiarity and expertise with at-least one of the high speed interfaces such PCIe Gen6/7, DDR5/LPDDR5, ONFI, USB3.2/USB4 etc.
• Minimum 8–12 years of relevant experience in SI/PI analysis, board/package design, and use of modern simulation tools (Hspice, ADS, Cadence, HFSS, Siemens Advanced Solvers).
• Expertise in Power delivery network concepts and signal integrity analysis.
• Technical proficiency in S-parameter extraction, 3D modeling, system-level SI simulation, and IBIS model development.
• Programming skills in Perl, TCL, Shell, and C.
• Hands-on experience with industry-standard EDA tools (Cadence PowerSI, Agilent ADS, Allegro SIP, Ansys SIwave, Siemens Advanced Solver).
• Familiarity with CMOS process technologies and specifications of various I/Os.
• Comfortable working in Linux environments.
• Relevant certifications in SI/PI analysis, simulation tools, or hardware design (preferred).

We're Expanding!
Engineer with strong hardware and process knowledge with major semiconductor OEM Etch tool is preferred.

Job Purpose

The Senior/Staff Process Engineer develops plasma etch processes for Memory/ Logic/ TSV/MEMS in oxide, dielectric and glass applications in support of our sales activities to customers, during installation and after service care. Their main duties include process testing and monitoring of the equipment, updating current system processes and conducting assessments of the working condition of our tools.

Principal Accountabilities

1. Develop new plasma etch processes for Memory/ Logic/ TSV/MEMS in oxide, dielectric and glass applications
2. Work with customer to maintain & optimize current plasma etch processes, including coordinating and conducting etch process demo
3. Qualify etch processes in installed base
4. Work with engineering and product group for continuous improvement project
5. Participate in customer meetings, escalations and resolve customer problems in a timely manner
6. Troubleshoot process issues
7. Keep field operations and management team informed of customer’s evaluation and perception of system performance
8. Provide technical guidance to less experienced process engineers and/or customer
9. Any other ad-hoc duties / projects assigned by Manager and Management

Education & Experiences

• Min. Bachelor's Degree in Engineering or related field. Exceptional candidates with significant experience may also be considered.
• Must have min. 3 years of relevant experience in wafer fab, either as part of Semiconductor Process Development or R&D team. At least 2 years previous experience hands-on knowledge on Etch process/equipment preferred.

Other Essential Attributes

• Independent and willing to accept challenges
• Willing to travel both regionally and internationally to support overseas installed base
• Flexibility to work on shift/ overtime/ stand-by/ on-call/ holidays when required
• Bilingual in English and Mandarin as counterparts are mostly Chinese speaking

Only shortlisted candidates will be contacted.

Please note that we will only accept direct applications on this job posting, emailed CVs will not be considered for the role.