Total 5 process development engineer job vacancies in Others category in Kodaira

・アナログ設計チームの一員として、新製品の開発を担当。
・システム・デジタル・レイアウトチームと連携しながらの1chip 開発。
・LDO、バンドギャップ、チャージポンプ、プリドライバー、パワーFET、ADCなどの回路を含む機能的ハイサイドスイッチアナログ製品への参加。
・最新のシミュレーション・検証ツールを使っての回路検証。

・Work within the analog design team for new product development;
・Work closely with system, digital, and layout teams with chip implementation
・Participate in functional high-side switch analog product lines, including blocks such as LDOs, Bandgaps, Charge pumps, Predrivers, Power FETs and ADCs.
・Verification of performance requirements using appropriate simulation and verification tools. 

As an AI Compiler Engineer on the Renesas HPC team, you will be responsible for driving compiler and code generation technologies that unlock the full compute potential of Renesas next-generation automotive System-on-Chip platforms, including advanced 3 nm silicon for software-defined vehicles (SDVs). Your work will directly impact how AI workloads — from perception and sensor fusion to in-vehicle assistants and advanced driver assistance — are translated into highly optimized, safe, and power-efficient execution on Renesas hardware.
This role bridges software compiler development, AI model lowering/optimization, and hardware-software co-design, enabling Renesas SoCs to deliver industry-competitive performance, efficiency, and functional safety required by multi-domain automotive applications..

【Job Description】
・Lead AI compiler architecture across model ingestion, graph optimization, lowering, code generation, and runtime integration
・Design and implement graph‑level optimizations (operator fusion, quantization‑aware rewrites, memory‑aware scheduling, partitioning)
・Drive performance optimization for target NPUs, including tiling, tensor layout, and multi‑core execution strategies
・Partner with SoC and AI accelerator architects to influence hardware features through compiler insights
・Own performance KPIs for real automotive AI workloads using simulators, profilers, and silicon‑correlated models
・Ensure compiler outputs meet automotive requirements (real‑time behavior, determinism, quality expectations)
・Mentor senior engineers and set technical direction without people‑management responsibilities

【Impact & Differentiators】
Renesas’ Gen5 R-Car automotive SoC lineup, including flagship 3 nm devices like the R-Car X5H, is among the first highly integrated multi-domain automotive SoCs built on advanced 3 nm process technology, designed to run ADAS, IVI, gateway, and next-gen SDV workloads on a centralized platform. These platforms deliver high AI performance (e.g., multi-hundreds of TOPS), scalable chiplet-based acceleration, and power efficiency tailored for electrified and autonomous vehicles while meeting stringent functional safety standards.  An AI Compiler Engineer enables this hardware vision by ensuring that state-of-the-art AI models and computational kernels are efficiently mapped to the silicon fabric — directly enhancing performance, reducing latency and energy, and accelerating software adoption in automotive ecosystems where compute efficiency and safety are paramount.

As an AI Compiler Engineer on the Renesas HPC team, you will be responsible for driving compiler and code generation technologies that unlock the full compute potential of Renesas next-generation automotive System-on-Chip platforms, including advanced 3 nm silicon for software-defined vehicles (SDVs). Your work will directly impact how AI workloads — from perception and sensor fusion to in-vehicle assistants and advanced driver assistance — are translated into highly optimized, safe, and power-efficient execution on Renesas hardware.
This role bridges software compiler development, AI model lowering/optimization, and hardware-software co-design, enabling Renesas SoCs to deliver industry-competitive performance, efficiency, and functional safety required by multi-domain automotive applications..

【Job Description】
・Lead AI compiler architecture across model ingestion, graph optimization, lowering, code generation, and runtime integration
・Design and implement graph‑level optimizations (operator fusion, quantization‑aware rewrites, memory‑aware scheduling, partitioning)
・Drive performance optimization for target NPUs, including tiling, tensor layout, and multi‑core execution strategies
・Partner with SoC and AI accelerator architects to influence hardware features through compiler insights
・Own performance KPIs for real automotive AI workloads using simulators, profilers, and silicon‑correlated models
・Ensure compiler outputs meet automotive requirements (real‑time behavior, determinism, quality expectations)
・Mentor senior engineers and set technical direction without people‑management responsibilities

【Impact & Differentiators】
Renesas’ Gen5 R-Car automotive SoC lineup, including flagship 3 nm devices like the R-Car X5H, is among the first highly integrated multi-domain automotive SoCs built on advanced 3 nm process technology, designed to run ADAS, IVI, gateway, and next-gen SDV workloads on a centralized platform. These platforms deliver high AI performance (e.g., multi-hundreds of TOPS), scalable chiplet-based acceleration, and power efficiency tailored for electrified and autonomous vehicles while meeting stringent functional safety standards.  An AI Compiler Engineer enables this hardware vision by ensuring that state-of-the-art AI models and computational kernels are efficiently mapped to the silicon fabric — directly enhancing performance, reducing latency and energy, and accelerating software adoption in automotive ecosystems where compute efficiency and safety are paramount.

As an AI Compiler Engineer on the Renesas HPC team, you will be responsible for driving compiler and code generation technologies that unlock the full compute potential of Renesas next-generation automotive System-on-Chip platforms, including advanced 3 nm silicon for software-defined vehicles (SDVs). Your work will directly impact how AI workloads — from perception and sensor fusion to in-vehicle assistants and advanced driver assistance — are translated into highly optimized, safe, and power-efficient execution on Renesas hardware.
This role bridges software compiler development, AI model lowering/optimization, and hardware-software co-design, enabling Renesas SoCs to deliver industry-competitive performance, efficiency, and functional safety required by multi-domain automotive applications..

【Job Description】
・Lead AI compiler architecture across model ingestion, graph optimization, lowering, code generation, and runtime integration
・Design and implement graph‑level optimizations (operator fusion, quantization‑aware rewrites, memory‑aware scheduling, partitioning)
・Drive performance optimization for target NPUs, including tiling, tensor layout, and multi‑core execution strategies
・Partner with SoC and AI accelerator architects to influence hardware features through compiler insights
・Own performance KPIs for real automotive AI workloads using simulators, profilers, and silicon‑correlated models
・Ensure compiler outputs meet automotive requirements (real‑time behavior, determinism, quality expectations)
・Mentor senior engineers and set technical direction without people‑management responsibilities

【Impact & Differentiators】
Renesas’ Gen5 R-Car automotive SoC lineup, including flagship 3 nm devices like the R-Car X5H, is among the first highly integrated multi-domain automotive SoCs built on advanced 3 nm process technology, designed to run ADAS, IVI, gateway, and next-gen SDV workloads on a centralized platform. These platforms deliver high AI performance (e.g., multi-hundreds of TOPS), scalable chiplet-based acceleration, and power efficiency tailored for electrified and autonomous vehicles while meeting stringent functional safety standards.  An AI Compiler Engineer enables this hardware vision by ensuring that state-of-the-art AI models and computational kernels are efficiently mapped to the silicon fabric — directly enhancing performance, reducing latency and energy, and accelerating software adoption in automotive ecosystems where compute efficiency and safety are paramount.

Renesas HPC チームの AI コンパイラエンジニアとして、次世代 3nm プロセスを含む Renesas の自動車向け次世代 SoC プラットフォームにおいて、その計算能力を最大限に引き出す コンパイラおよびコード生成技術の開発を担っていただきます。

本ポジションでは、知覚処理、センサーフュージョン、車載アシスタント、先進運転支援（ADAS）などの AI ワークロードを、Renesas ハードウェア上で高度に最適化し、安全かつ省電力に実行可能な形式へ変換するプロセスに直接貢献いただきます。

ソフトウェアコンパイラ開発、AI モデルのロワリング／最適化、ハードウェア・ソフトウェア共設計の領域を横断し、マルチドメイン自動車アプリケーションに求められる業界競争力のある性能・効率・機能安全を Renesas SoC で実現する、技術的中核となる役割です。

【Job Description】

• モデル入力から、グラフ最適化、ロワリング、コード生成、ランタイム統合までを含む AI コンパイラアーキテクチャの設計および技術リード
• オペレータ融合、量子化対応リライト、メモリ考慮型スケジューリング、パーティショニングなどの グラフレベル最適化の設計・実装
• 対象 NPU 向けの 性能最適化（タイル化、テンソルレイアウト設計、マルチコア実行戦略 等）の推進
• SoC／AI アクセラレータアーキテクトと密に連携し、コンパイラ視点からハードウェア機能の方向性に影響を与える技術提案
• シミュレータ、プロファイラ、シリコン相関モデルを活用した 実車載 AI ワークロードにおける性能 KPI の定義および評価
• コンパイラ出力が **自動車要件（リアルタイム性、決定性、品質・安全基準）**を満たすことの保証
• 直接的なピープルマネジメントは伴わないものの、シニアエンジニアへのメンタリングおよび技術的方向性の提示

【Impact & Differentiators】

Renesas の Gen5 R-Car 自動車向け SoC ラインアップ（フラッグシップとなる 3nm デバイス R-Car X5H を含む）は、ADAS、IVI、ゲートウェイ、次世代 SDV ワークロードを 集中型プラットフォームで実行することを目的に設計された、業界初期の高度統合マルチドメイン自動車 SoC です。

これらのプラットフォームは、

• 数百 TOPS クラスの高い AI 演算性能
• スケーラブルなチップレットベースのアクセラレーション
• 電動化・自動運転車に求められる優れた電力効率
• 厳格な機能安全要件への対応

といった特長を備えています。

AI コンパイラエンジニアは、最先端の AI モデルや計算カーネルを シリコン上に最適にマッピングすることで、このハードウェアビジョンを具現化し、性能向上、レイテンシおよび消費電力の削減、ソフトウェアエコシステムの採用加速に直接貢献します。
計算効率と安全性が極めて重要な自動車エコシステムにおいて、不可欠かつ高い影響力を持つポジションです。