Total 74 Engineering job vacancies in bengaluru

We are looking for an Embedded Storage Firmware Engineer to design, develop, and maintain firmware for high performance storage devices and controllers. In this role, you will work close to the hardware, building reliable, high‑performance firmware that manages data movement, flash media, and device behavior under real‑world workloads.

You will contribute across the storage firmware stack, including boot, device initialization, data path, error handling, diagnostics, performance optimization, and reliability features, working closely with hardware, validation, and system teams.

Key Responsibilities

Storage Firmware Development

• Design and implement embedded firmware for storage devices such as SSDs or storage controllers.
• Develop firmware modules for device initialization, command processing, and data movement.
• Implement and maintain state machines and control logic for reliable storage operation.
• Implement recovery mechanisms to ensure data integrity and device reliability.
• Optimize firmware for throughput, latency, and power efficiency.
• Analyze and improve performance under various workloads.
• Add robust error detection, logging, and recovery mechanisms.
• Develop low‑level drivers and hardware interfaces as required.
• Support firmware integration with host software and system drivers.
• Debug complex firmware and hardware interaction issues using JTAG, logs, traces, and emulation/simulation tools.
• Collaborate with validation teams to reproduce, analyze, and fix issues.
• Support bring‑up and stabilization on new platforms and silicon revisions.

Looking for a 5+ years experienced Engineer with good understanding of Analog concepts, experience of from scratch design of key analog blocks, integrating smaller blocks to create functional I/Ps and full ownership of those, ICs and well versed with Transistor level design flow, to join the 2.6B$ Power Business Unit. The candidate will get to work on a wide range of exciting products such as PMICs, Linear and Switching DC-DC converters powering the next generation of most sought-after phones and hand held devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.

Essential Functions:

• Must be proficient in designing and owning key analog blocks including Bangdap references, Analog Buffers, Op-Amps, Comparators, High speed level shifters etc.
• Must be able to come up with architectures to meet block level performance specifications.
• Must be well versed of the standard architectures and be able to bring in innovative ideas to improve designs to meet challenging specifications.
• Should have clear understanding of analog layouts and should be able to work closely with and guide layout engineers to ensure quality layout to meet the desired performance.
• Must be conversant with the standard design, extraction and simulation flows & tools, speed, convergence, accuracy trade-offs and should be able to optimize setups based on Pre/Post (with/without) Parasitic using simulator options, debug and navigate through tool related challenges.
• Should be able to mentor Freshers and Junior engineers for upscaling their technical skills as well as other skills needed for better efficacy.
• Should be able to develop multiple blocks with minimal supervision, take full ownership to drive all aspects within committed schedule and work closely with Sr members of Design team to support them build subsystem/chip top.
• Experience of silicon validation and debug is a strong advantage.
• Should have good understanding of ESD and be able to design the I/O ring for the IC

The Cloud Infrastructure Networking Engineer is responsible for designing and implementing the enterprise data architecture. This role will lead the development of scalable, secure, and integrated data platforms to support analytics, compliance, and business operations.

This role will be the cloud networking authority for the AWS environment. This role owns the design, operations, and reliability of everything from VPC architecture and firewall policy to remote access and infrastructure automation. This role also brings strong systems-engineering instincts: incident leadership, monitoring hygiene, and the drive to reduce operational toil over time.

This is a high-autonomy individual contributor role. This role sets direction for networking decisions, make the calls, and drive execution. This role will partner closely with Security and platform engineering, and own the networking domain

Responsibilities

AWS Cloud Networking

• Design and operate VPCs, subnets, routing, segmentation, ingress/egress patterns, security boundaries, and VPC endpoints/PrivateLink-style connectivity
• Define scalable networking standards that make workload onboarding consistent, secure, and repeatable
• Troubleshoot complex connectivity issues across AWS: routing, access controls, DNS resolution patterns

Palo Alto Firewalls & GlobalProtect

• Administer Palo Alto firewall policy lifecycle: safe changes, segmentation strategy, troubleshooting
• Own GlobalProtect remote access operations, stability, access controls, incident response
• Partner with Security to ensure network controls align with risk posture and audit expectations

Infrastructure as Code & Automation

• Build and maintain AWS networking and firewall infrastructure using Terraform (reusable modules, reviewable changes, controlled rollouts)
• Build and maintain GitHub Actions workflows for infrastructure CI/CD (plan/apply gating, workflow reliability)
• Automate operational tasks with Python and Bash (PowerShell is a plus)

Operational Excellence

• Support production infrastructure across Linux and Windows (patching, hardening, reliability improvements)
• Participate in on-call rotation and lead incident response for infrastructure and connectivity issues
• Improve monitoring, alerting, and operational visibility to catch issues earlier
• Drive root-cause analysis and prevention work to reduce repeat incidents

We are looking for an Embedded Storage Firmware Engineer to design, develop, and maintain firmware for high performance storage devices and controllers. In this role, you will work close to the hardware, building reliable, high‑performance firmware that manages data movement and device behavior under real‑world workloads.

You will contribute across the storage firmware stack, including boot, device initialization, data path, error handling, diagnostics, performance optimization, and reliability features, working closely with hardware, validation, and system teams.

Key Responsibilities

Storage Firmware Development

• Design and implement embedded firmware for storage devices such as SSDs or storage controllers.
• Develop firmware modules for device initialization, command processing, and data movement.
• Implement and maintain state machines and control logic for reliable storage operation.
• Implement recovery mechanisms to ensure data integrity and device reliability.
• Optimize firmware for throughput, latency, and power efficiency.
• Analyze and improve performance under various workloads.
• Add robust error detection, logging, and recovery mechanisms.
• Develop low‑level drivers and hardware interfaces as required.
• Support firmware integration with host software and system drivers.
• Debug complex firmware and hardware interaction issues using JTAG, logs, traces, and emulation/simulation tools.
• Collaborate with validation teams to reproduce, analyze, and fix issues.
• Support bring‑up and stabilization on new platforms and silicon revisions.

We are seeking a Security Firmware Engineer to design, implement, and maintain security‑critical components in embedded firmware for next‑generation storage and controller products. This role focuses on device‑level security, including secure firmware update, lifecycle management, debug port control, Root of Trust (RoT) interactions, and protection of critical assets such as keys, OTP, and credentials.

The ideal candidate has strong low‑level firmware expertise combined with hands‑on experience in embedded security architectures and secure system design.

Key Responsibilities

Security Firmware Architecture & Development

• Design and implement security layers within device firmware, aligned with product security requirements and ASIC security IP capabilities
• Integrate firmware with Root of Trust (RoT) subsystems, including support for both hardware‑based and firmware‑based RoT models where applicable. 
• Ensure secure handling of cryptographic material and prevention of unauthorized access.
• Implement and integrate cryptographic primitives and related authentication and encryption flows used in firmware
• Work closely with hardware teams to leverage ASIC security IPs, HSMs, and secure key storage.
• Support security testing, threat analysis, and vulnerability mitigation during development and validation cycles.
• Participate in design reviews, security assessments, and risk evaluations.

We are seeking a deep technical Technologist to join our Firmware Engineering team, focusing on the core, low-level firmware for our next-generation flash project. You will be a key player in implementing the firmware that directly interacts with the NAND memory, manages system power and thermals. This is a hands-on role for a problem-solver who can ensure the performance, reliability, and efficiency of our flash storage solutions.

Key Responsibilities

• NAND Flash Firmware: Design and implement the firmware that directly controls and accesses the flash memory. This includes developing drivers for high-speed flash interfaces and designing algorithms for raw data access, error correction, and wear leveling at the physical layer.
• Power & Thermal Management: Lead the design and implementation of intelligent firmware for low-power states, dynamic voltage and frequency scaling (DVFS), and thermal throttling. You will be responsible for optimizing power consumption and managing the thermal profile of the controller under various workload conditions.
• Debug & Optimization: Utilize your expertise to debug complex, system-level issues related to NAND access, power, thermal, and memory subsystems. You'll profile and optimize the firmware to squeeze out every bit of performance and efficiency.
• Cross-Functional Collaboration: Work closely with the hardware, ASIC, and verification teams to define requirements and debug issues, ensuring a cohesive and high-performing system.

About the position:

As a Staff firmware verification engineer, you will be part of firmware verification team that design and develop white box and grey box tests in Python to verify SSD firmware designs for each firmware feature. This position is specifically to focus on verification and validation of SSD firmware features. You will be working closely with product architects and firmware engineers to create a comprehensive firmware verification test for SSD features. In this role, you will be contributing to test strategy, test development, integrating the tests using various development platforms, deploying it on firmware verification lab for regression runs and perform failure analysis. The role focuses on defining and executing robust firmware verification strategies for PCIe, MMIO, DMA, and custom host–device protocols across both pre‑silicon and post‑silicon environments.

Responsibilities:

• Collaborate closely with firmware engineers & architects on product architecture and designs to define the comprehensive verification plan to validate each SSD features
• Design, Develop and Integrate the white box and gray box tests on SSD products in roadmap
• Conduct test plan reviews and code reviews to ensure the tests are scalable and meeting the requirements
• Participate in driving failure analysis and collaborate with integration/execution engineers for test deployment.
• Validate designs against PCI Express Base Specification (up to Gen5/Gen6), ensuring compliance with electrical, logical, and transaction-layer requirements.
• Define and own firmware validation strategy for PCIe front-end subsystems, including MMIO address spaces, BARs, resets, interrupts, and error handling.
• Define, plan, and execute system-level validation strategies for PCIe front-end (PHY + controller) IP and SoC-level integration.
• Integrate tests into scalable automation frameworks supporting simulation, emulation, and silicon validation.
• Debug firmware issues, perform front-end error injection, and expose design or integration defects.
• Validate PCIe compliance, MMIO access integrity, and robustness of fault detection and recovery mechanisms.
• Review and verify firmware trace logs and debug telemetry for correctness and completeness.
• Drive validation readiness across pre‑silicon and post‑silicon platforms, ensuring alignment of firmware specs, drivers, and test collateral.
• Interface with cross‑functional stakeholders to ensure validation coverage meets product and customer requirements.
• Drive compliance and interoperability testing with various endpoint/root-complex devices, switches, and add-in cards.

We seek an experienced IT professional to join us as a Staff Site Reliability Engineer, working in the Product Reliability Engineering function who will:

• Perform day-to-day site reliability engineering functions including Maintenance and incident resolution for all Debit applications, products, and services – including debit, prepaid and risk lines of business.
• Perform ongoing/Proactive analysis of various debit authorization, Api and UI based applications to detect potential problems and actively engage & facilitate the discussion to find the best possible solution.
• Work under the Guidance of technical subject matter experts and be point of contact for key DPS projects.
• Work closely with service partners such as product development, engineering teams to seamlessly implement the innovative solutions to improve the reliability, scalability, and efficiency.
• Contribute towards automating the routine tasks and processes to improve overall efficiency and reduce human errors.
• Actively participate in troubleshooting activities and SWAT calls and drive investigation towards swift resolution.
• Participate in the Major Problem Review discussions, drive the root cause analysis, identify the gaps, and come up with innovative preventive measures.
• Mentor junior team members and foster a culture of continuous improvement in the team through retrospectives and open feedback.
• Build comprehensive and robust documentation repositories that can facilitate knowledge transfer among DPS PRE and DPS Global Operations peers.
• Implement innovative GenAI and machine learning trends to continuously optimize the application reliability and efficiency.  
• Work with observability team to design and implement the modern visa observability solutions such as Anomaly detection, operations intelligent platform (OIP), Fault Isolation tool (FIT) across all DPS products.
• Provide on-call support in 12*7 model.   
• Self-motivated, and have excellent interpersonal and communication skills.

This is a hybrid position. Expectation of days in the office will be confirmed by your Hiring Manager. 

Visa’s Technology Organization is a community of problem solvers and innovators reshaping the future of commerce.   We operate the world’s most sophisticated processing networks capable of handling more than 65k secure transactions a second across 80M merchants, 15k Financial Institutions, and billions of everyday people.   While working with us you’ll get to work on complex distributed systems and solve massive scale problems centered on new payment flows, business and data solutions, cyber security, and B2C platforms.     

The Opportunity: 

We are seeking a GenAI Architect / Sr Consultant, Software Engineer (I6.5) who is both a hands-on full-stack engineer and a team leader capable of designing, developing, and deploying GenAI‑powered applications. You will manage and mentor an engineering team while delivering scalable AI systems that integrate with Visa’s product ecosystem, developer platforms, and internal operational tools.

This role blends architecture, leadership, full-stack development, cloud engineering, and GenAI frameworks.  As a Visa Lead Engineer, you will be an integral part of a multi-functional development team inventing, designing, building, and testing software products that reach a truly global customer base. While building components of powerful payment technology, you will get to see your efforts shaping the digital future of monetary transactions.   

The Work itself: 

• Global Operations holds the responsibility of ensuring Visa’s diverse portfolio of commercial services are performing optimally, meeting stringent availability targets and exceeding our clients’ expectations.  
• By architecting automation and GenAI into our operational DNA, and deeply embedding AIOps into our strategic foundation, Global Operations, the engine room of production operations, is well positioned to think big, act quickly and innovate with intention. 
• Working with highly integrated, high-throughput systems, an equally high importance must be placed on robust observability, intelligent event detection and incident management.  
• Global Operations sets the operational standards to support the business demands of today and the operational needs of tomorrow as technologies continue to evolve and adjust the way we work to support the business.  
• Through blame free post mortems, intellectual curiosity and problem solving we turn reactive into proactive and create an environment that provides the support and mentorship for our team members to learn and grow. 

This is a hybrid position. Expectation of days in the office will be confirmed by your Hiring Manager. 

Our project is to provide visual solution to investigate and query all data from our platform for customers using Nexthink Query Language (NQL) behind the scene hiding the complexity of the language. For that we developed Visual Editor, Rich data table with actions over data, and for more advanced queries we provide NQLEditor build on top of Monaco Editor.

Our technology stack:

Java, Micronaut Framework, ReactJs/Typescript, GraphQl, RestAPI, gRPC….

• Design, implement, deliver and validate product features
• Help improving the team architecture, design and development best practices
• Handle L3 support requests (together with the rest of the team)
• Participate actively in the technology roadmap
• Work with the agile iterative/incremental mindset and best practices and participate actively to the different ceremonials

Job Description: 

• Should be good in understanding the PCB board’s w.r.t layout schematics and information about the various active and passive components on the PCB.
• Good hands on BOM analysis and report preparation.
• Excellent debugging and Failure Analysis skills with exposure to tools like protocol analysers, Logical analysers, CRO etc. Should be good at reproducing and root causing the issues.
• Good Power analysis and Power tree Distribution Reverse engineering skills
• Good to have Experience in Storage Domain.
• Good to have Knowledge on the PCB Construction and Assembly details
• Good Experience in System level activities for hardware design and validation.
• Good to have Experience working with Flash memory technologies and internals.
• Good to have Experience in NVMe, SD/uSD, USB or PCIE protocols understanding.
• Mindset towards delivering the Highest Quality product to the customer.
• Must be execution focused, have zeal to learn more and do more. Take initiatives.
• Proven ability to achieve results in a fast moving, dynamic environment.
• Should be good team player, approachable with to do attitude.

Duties:

• Solve highly complex technical problems and deliver innovative, scalable, and maintainable solutions with minimal supervision.
• Implement architectural patterns and design standards, collaborating closely with key stakeholders to ensure adherence to defined architecture and best practices.
• Champion efficient and effective software development methodologies aligned with Agile and Lean principles, fostering continuous learning, collaboration, and iterative improvement.
• Contribute hands-on to development by designing, coding, reviewing, and optimizing critical software components and services.
• Drive adoption of DevOps practices and toolchains with a strong emphasis on automation, continuous integration, continuous deployment, and proactive operational monitoring.
• Embed security, reliability, scalability, and performance considerations into architecture, design, and development processes as non-negotiable quality attributes.
• Demonstrate deep expertise in modern platforms, frameworks, and tools, leveraging open-source technologies and open standards where appropriate to optimize cost and flexibility.
• Promote and enforce secure coding practices and the integration of security controls throughout the Software Development Life Cycle (SDLC).
• Serve as a technical bridge between engineering, QA, and other teams to design efficient testing strategies and enable high-quality, innovative delivery outcomes.

Duties:

• Solve highly complex technical problems and deliver innovative, scalable, and maintainable solutions with minimal supervision.
• Implement architectural patterns and design standards, collaborating closely with key stakeholders to ensure adherence to defined architecture and best practices.
• Champion efficient and effective software development methodologies aligned with Agile and Lean principles, fostering continuous learning, collaboration, and iterative improvement.
• Contribute hands-on to development by designing, coding, reviewing, and optimizing critical software components and services.
• Drive adoption of DevOps practices and toolchains with a strong emphasis on automation, continuous integration, continuous deployment, and proactive operational monitoring.
• Embed security, reliability, scalability, and performance considerations into architecture, design, and development processes as non-negotiable quality attributes.
• Demonstrate deep expertise in modern platforms, frameworks, and tools, leveraging open-source technologies and open standards where appropriate to optimize cost and flexibility.
• Promote and enforce secure coding practices and the integration of security controls throughout the Software Development Life Cycle (SDLC).
• Serve as a technical bridge between engineering, QA, and other teams to design efficient testing strategies and enable high-quality, innovative delivery outcomes.

Job Description: 

• Should be good in understanding the PCB board’s w.r.t layout schematics and information about the various active and passive components on the PCB.
• Good hands on BOM analysis and report preparation.
• Excellent debugging and Failure Analysis skills with exposure to tools like protocol analysers, Logical analysers, CRO etc. Should be good at reproducing and root causing the issues.
• Good Power analysis and Power tree Distribution Reverse engineering skills
• Good to have Experience in Storage Domain.
• Good to have Knowledge on the PCB Construction and Assembly details
• Good Experience in System level activities for hardware design and validation.
• Good to have Experience working with Flash memory technologies and internals.
• Good to have Experience in NVMe, SD/uSD, USB or PCIE protocols understanding.
• Mindset towards delivering the Highest Quality product to the customer.
• Must be execution focused, have zeal to learn more and do more. Take initiatives.
• Proven ability to achieve results in a fast moving, dynamic environment.
• Should be good team player, approachable with to do attitude.

Role Summary:

We are seeking a Software Engineer to contribute to the development of AI/ML software for our AI Privacy Box platform. This role involves implementing and optimizing LLM and RAG workflows, with a focus on efficient use of storage and system resources.

Key Responsibilities:

• Develop AI/ML software components for the AI Privacy Box platform.
• Implement and integrate LLM and RAG models into the software stack.
• Work on performance optimization of AI workloads using storage and system‑level techniques.
• Contribute to system software components interacting with OS, memory, and I/O subsystems.
• Collaborate with senior engineers on architecture, design, and optimization.
• Debug, test, and maintain high‑quality, production‑ready code.

Required Skills:

• Knowledge of Machine Learning and AI/ML fundamentals.
• Exposure to LLMs and RAG concepts or frameworks.
• Proficiency in C and/or C++.
• Understanding of Operating Systems concepts.
• Strong knowledge of Data Structures and Algorithms.