Total 14 technology development job vacancies in Engineering category in Bengaluru

• Providing technical leadership and expertise to define requirements for framework through programming/scripting of verification and emulation flows.
• Partnering with ASIC engineers to deploy and support framework for technologies like advanced verification environment configuration and management.
• Collaborating cross-functionally to optimize verification and emulation workflows and standardize methodologies.

• Development of C++/SystemC models for complex ASIC IPs, SOCs and Flash Memories.
• Create System Level Tests and/or Standalone Unit Tests and verify the models.
• Lead and Guide team in the project activities.
• Keen on schedule and quality of the deliverables.
• Timely support to the stakeholders enabling software bring-up.

As a Pricipal Emulation Engineer in the ASIC Emulation team, you will be responsible for Emulation builds, sanity test suite & methodology. 

• Providing technical leadership and expertise to define requirements for Emulation and Emulation IP development.
• Create emulation models from RTL / Netlist. Develop hardware collateral to be integrated with the Palladium / FPGA emulation mode.
• Experience in Palladium or Zebu Platforms Automation and increase process efficiencies.
• Collaborating cross-functionally to optimize emulation workflows and standardize methodologies.
• Work with extended teams to debug environment and drive cross-functional testing (Firmware, Software, Verification and Design)
• Triage failures with design, verification, firmware, software teams.
• Mentoring and guiding junior engineers, fostering a culture of collaboration, innovation and continuous improvement.

Skills Required:

• Working knowledge of Linux/Unix environment and shell scripting
• Excellent debugging and problem-solving skills with simulation and emulation environments.
• Cross-Functional Collaboration: Ability to work closely with design, validation, firmware, and physical design teams to resolve system-level issues.
• Strong team player, able to collaborate effectively across architecture, design, and validation teams.

Experience in ASIC verification, Expertise in System Verilog and UVM, Verilog.

·        Experience in IP level verification, testbench architecture development, Testbench component developments. Expertise in coverage closer, code coverage, functional coverage Experience in Gate level simulations.

·        The candidate should be able to define verification plan, create testbenches, testcases,gate level simulations etc independently.

·        Knowledge on serial protocols UFS, PCIe, USB, MIPI or any other serial protocol. Knowledge on memory protocols - AXI, PCIE, UFS and Flash etc.

·        Knowledge on scripting languages like Python, Perl etc.

·        Keen on continuous process improvement to improve Quality and time

The SoC Development team is seeking highly motivated engineers to join a team of experienced engineers working on the development of controller SoCs.

As a Verification Engineer in SoC Development Team, you will develop test-plans and tests for use in testing complex hardware in System On Chip (SoC) ASIC’s.  Your work will enable industry-leading data storage control SoC’s that get deployed into high volume consumer and enterprise products.

The growing diversity of data creates an exponential number of new possibilities – for the world, our company and you. You’ll be part of a team driving the innovations necessary to outpace new demands and challenges everywhere data lives, from sensors to mobile devices to the cloud. We’ve only started to scratch the surface of what data can do. You can help unlock its full potential.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Responsible for driving verification strategy, creating Test Plans, and developing Test Benches for SoC.
• Collaborate with architects, designers,  pre-and post-silicon verification teams to develop test plans
• Responsible to develop C-based tests on SoC. Processor knowledge is a plus.
• Define and meet all functional coverage goals
• Run and debug gate-level simulations 
• Understanding and generation of functional patterns for ATE

SoC Verification Engineer

The SoC Development team at Sandisk is seeking highly motivated SoC Verification Engineers to join our talented team, working on cutting-edge controller development for high-performance SoCs used in industry-leading products.

Role & Responsibilities:

As a SoC Verification Engineer, you will play a key role in ensuring the quality and reliability of our SoC designs. You will be responsible for:

• Developing verification test plans based on design specifications.
• Creating and executing test cases across multiple platforms, including RTL simulation, FPGA prototyping, and Palladium emulation.
• Verification test structures (DFx Verification)
• Performing Gate-Level Simulations (GLS) and debugging complex SoC designs.
• Collaborating with design, architecture, and firmware teams to define verification strategies and drive coverage-driven verification methodologies.
• Contributing to the development of advanced verification environments, including UVM, PSS testbenches.
• Analyzing functional coverage and simulation results to enhance verification efficiency and effectiveness.
• Genrating Fucntional patterns required for Wafer Sorting. 

Why Join Us?

At Sandisk, you’ll be part of a team of highly skilled engineers solving complex verification challenges and driving innovations in data storage solutions. Your work will directly impact the performance and reliability of high-volume new age data solutions, consumer and enterprise products.

Together, we’ll push the boundaries of technology, unlock the full potential of data, and shape the future of storage solutions.

The SoC Development team is seeking highly motivated engineers to join a team of experienced engineers working on the development of advanced controller SoCs.

As a Technologist Verification Engineer in the SoC Development Team, you will be responsible for planning, architecting, and executing verification strategies to validate complex hardware in System-on-Chip (SoC) ASICs. Your work will enable industry-leading data storage control SoCs deployed into high-volume consumer and enterprise products.

The growing diversity of data creates an exponential number of new possibilities – for the world, our company, and you. You’ll be part of a team driving the innovations necessary to outpace new demands and challenges everywhere data lives, from sensors to mobile devices to the cloud. We’ve only started to scratch the surface of what data can do. You can help unlock its full potential.

Essential Duties and Responsibilities

• Ownership: End-to-end ownership of one or more subsystems or SoC verification flows, including planning, execution, and closure
• Mentorship: Experience mentoring junior and mid-level engineers, reviewing their test plans, code, and coverage.
• Define verification strategy, create detailed test plans, and develop robust test benches for SoC verification.
• Collaborate with architects, RTL designers, and pre- and post-silicon verification teams to ensure end-to-end verification coverage.
• Develop and run UVM/SystemVerilog-based verification environments.
• Write, run, and debug C-based tests on SoCs; processor and embedded software knowledge is a must.
• Define and achieve functional and code coverage goals; track and close coverage gaps.
• Run, debug, and sign off gate-level simulations with SDF annotation.
• Develop and validate functional patterns for ATE (Automatic Test Equipment).
• Debug complex issues across multiple domains (digital logic, firmware, timing, DFT).
• Participate in IP and subsystem-level integration verification and ensure smooth transition to SoC-level verification.
• Support low-power verification using UPF and ensure power intent validation.
• Automate regression setup, execution, and result analysis using scripting languages (Python, Perl, TCL, etc.).
• Contribute to verification methodology improvements, reusable environments, and verification infrastructure scalability.
• Work closely with validation and bring-up teams to ensure test portability from pre-silicon to post-silicon.

As a SoC Validation/Verification Engineer, you will play a key role in ensuring the quality and reliability of our SoC designs. You will be responsible for:

• Understanding complex ASIC specifications to create comprehensive Verification/Validation plans for both pre- and post-silicon validation.
• Independently developing and executing tests for verification and validation.
• Collaborating with cross-functional teams to drive closure of verification and validation activities.
• Signing off on verification and validation deliverables.
• Debugging and root cause analysis of issues found during validation.
• Developing and maintaining automated test environments and regression suites.
• Contributing to the continuous improvement of verification methodologies and best practices.

Your work will enable industry-leading data storage control SoCs that are deployed in high-volume consumer and enterprise products.

Why Join Us?

At SanDisk, you’ll be part of a team of highly skilled engineers solving complex verification challenges and driving innovation in data storage solutions. Your work will directly impact the performance and reliability of next-generation data solutions for both consumer and enterprise markets.

Together, we’ll push the boundaries of technology, unlock the full potential of data, and shape the future of storage solutions.

• Development of C++/SystemC models for complex ASIC IPs, SOCs and Flash Memories.
• Create System Level Tests and/or Standalone Unit Tests and verify the models.
• Lead and Guide team in the project activities.
• Keen on schedule and quality of the deliverables.
• Timely support to the stakeholders enabling software bring-up.

We are looking for technically sound and highly skilled Analog/High Speed DDR IO Layout designer with 8-12 years of experience. The ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems.

Key Responsibilities:

• Develop and optimize MSIP IC layouts in TSMC 3nm, ensuring high performance and manufacturability.
• Collaborate with design engineers to understand design requirements and translate them into precise layouts.
• Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently.
• Work closely with the physical design team to integrate custom blocks into the overall chip design.
• Identify and resolve layout-related issues, providing creative solutions to meet design specifications.
• Conduct design reviews and provide technical feedback to improve layout practices and methodologies.
• Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes
• Any prior AI knowledge/experience which can improve Layout development effort and QoR is a big plus

Qualifications

• 8-12 years of experience in Analog/High Speed DDR IO IC layout design.
• Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics.
• Hands-on experience with custom layout design for Analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, High speed DDR IOs.
• Familiarity with custom digital layout (i.e. high speed logic paths).
• Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding).
• Strong understanding of analog/IO design principles, including circuit performance and parasitic effects.
• Aware of layout techniques to mitigate ESD, latch-up issues.
• Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below.
• Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating.
• Experience with layout optimization for power, performance, and area (PPA) metrics.
• Excellent problem-solving skills and attention to detail.
• Effective communication and teamwork abilities.

Preferred Skills:

• Knowledge of scripting languages (e.g., Skill,TCL and SVRF) for automation tasks.

• Work as one of  the senior team members or as lead of analog IPs and deliver analog blocks on-time with state-of-the-art architecture to meet the overall product requirements
• Work closely with team in designing and delivering analog blocks
• Design analog modules from scratch
• Handling assigned tasks independently
• Pro-actively get design issues/problems resolved
• Contribute to or propose innovative design solutions and design methodologies
• Work closely with the layout engineers on providing requirements and guidelines

The candidate to have a passion for complex processor architecture, digital design, and verification in general. The candidate should be team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. The candidate should have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:
 

• - EMIR closure at Tile /Partition/Subsytem/SOC level on a particular node
• Ownership of EMIR Flow & Signoff
• Drive EMIR closure for design blocks and full-chip integration.
• Align EMIR analysis phases with PD milestones (INIT, PREFINAL, FINAL).
• Ensure compliance with signoff limits provided by SIPI team for given technology node
• Ability to analyze EMIR violations and propose implementation choices.
• Familiarity with DFx and scan architecture for EMIR considerations.
• Technical Leadership

• Define EMIR signoff strategy, including IR drop and electromigration analysis.
• Review floorplan, clocking, and bus structures for IR hotspots.
• Coordinate bump allocation and power rail alignment with integration teams.
• Collaboration & Coordination
  • Work closely with block owners, PD team, and integration team to execute EMIR runs.
  • Conduct EMIR run reviews and debug sessions with stakeholders.
  • Methodology & Flow Development
    • Maintain and improve EMIR flow

    • Engage with SIPI team for current profile analysis and CPA/CPM models

PREFERRED EXPERIENCE:
 

• Minimum 13+  years of relevant work experience.
• Expertise in Synthesis , ICC2/ FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools.
• Expertise in Signoff tools like Ansys Redhawk/RHSC on EMIR, PT-PX for Power signoff and Primetime for Timing
• Should have worked as a go to person or technical lead for at least few full chip projects.
• Strong technical leadership and ability to mentor/guide/coach design engineers to achieve and deliver project goals.
• Strong inter-personal skills and ability to collaborate with teams spread across multiple geos.
• Should have good scripting experience in Shell, Python, Perl, TCL, UNIX along with decode/debug old existing scripts.
• Must be using AI technologies in day to day problem solving

We are looking for technically sound and highly skilled Analog/High Speed DDR IO Layout designer with 8-12 years of experience. The ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems.

Key Responsibilities:

• Develop and optimize MSIP IC layouts in TSMC 3nm, ensuring high performance and manufacturability.
• Collaborate with design engineers to understand design requirements and translate them into precise layouts.
• Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently.
• Work closely with the physical design team to integrate custom blocks into the overall chip design.
• Identify and resolve layout-related issues, providing creative solutions to meet design specifications.
• Conduct design reviews and provide technical feedback to improve layout practices and methodologies.
• Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes
• Any prior AI knowledge/experience which can improve Layout development effort and QoR is a big plus

Qualifications

• 8-12 years of experience in Analog/High Speed DDR IO IC layout design.
• Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics.
• Hands-on experience with custom layout design for Analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, High speed DDR IOs.
• Familiarity with custom digital layout (i.e. high speed logic paths).
• Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding).
• Strong understanding of analog/IO design principles, including circuit performance and parasitic effects.
• Aware of layout techniques to mitigate ESD, latch-up issues.
• Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below.
• Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating.
• Experience with layout optimization for power, performance, and area (PPA) metrics.
• Excellent problem-solving skills and attention to detail.
• Effective communication and teamwork abilities.

Preferred Skills:

• Knowledge of scripting languages (e.g., Skill,TCL and SVRF) for automation tasks.

Key Responsibilities

• Lead, mentor and deliver technical contributions for designing advanced high bandwidth ASIC packages.
• Conduct advanced power and signal integrity analysis for board and MCM packages.
• Provide expert design guidance for power distribution networks, collaborating with digital design, package, and board teams.
• Recommend and implement improvements to power and signal nets, enhancing overall system reliability.
• Perform circuit simulations using Hspice netlists and full-chip models.
• Develop and validate behavioral models (IBIS) for I/Os, supporting high-speed USB3/USB2 interfaces in integrated mobile platforms.
• Utilize industry-standard tools (Cadence PowerSI, 3DEFM, T2B, PowerDC, Agilent ADS, Nimbic, AllegroSIP) for analysis and design.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or related field.
• Familiarity and expertise with at-least one of the high speed interfaces such PCIe Gen6/7, DDR5/LPDDR5, ONFI, USB3.2/USB4 etc.
• Minimum 8–12 years of relevant experience in SI/PI analysis, board/package design, and use of modern simulation tools (Hspice, ADS, Cadence, HFSS, Siemens Advanced Solvers).
• Expertise in Power delivery network concepts and signal integrity analysis.
• Technical proficiency in S-parameter extraction, 3D modeling, system-level SI simulation, and IBIS model development.
• Programming skills in Perl, TCL, Shell, and C.
• Hands-on experience with industry-standard EDA tools (Cadence PowerSI, Agilent ADS, Allegro SIP, Ansys SIwave, Siemens Advanced Solver).
• Familiarity with CMOS process technologies and specifications of various I/Os.
• Comfortable working in Linux environments.
• Relevant certifications in SI/PI analysis, simulation tools, or hardware design (preferred).