Job Responsibilities:
At MediaTek’s Memory Design Automation team, we work seamlessly with worldwide memory design
teams to deliver high performance, low power and small area in-house memories design kits and design
flows under advanced technology nodes. We are looking for candidate to join us as memory design
automation engineer for the delivery of robust memory and development of Memory Compiler
automation flow.
• Delivering robust memory solutions.
• Developing Memory Compiler automation flows.
• Creating behavioral, FPGA, timing, and DFT simulation models.
• Debugging and optimizing SRAM models for ASIC design flows.
Requirements:
➢ Knowledge of high performance, low power SRAM/ROM and VLSI design is an added advantage.
Experience with EDA tools will be helpful.
➢ Proficient with Perl, Shell, Python, C/C++ languages, knowledge with AI machine learning
algorithm and infrastructure is an added advantage.
➢ Good understanding of verilog syntax and its various aspects, such as behavioral, RTL and
synthesizable verilog is a must.
➢ Good understanding of liberty timing syntax.
➢ Knowledge and experience with EDA simulation tools such as VCS, NC is required.
➢ Experience with EDA tools will be helpful:
o DFT: Logicvision, Tessent, Fastscan
o Synthesis: Design compiler, Genus
o Simulation tools:VCS, QuestaSim, NC
o STA tools such as PrimeTime
EA License No. 01C4394 • RCB No. 200007268E •EA Registration • Lim Jia Jie EA Registration No. R22108969
By sending us your personal data and curriculum vitae (CV), you are deemed to consent to PERSOL Singapore Pte Ltd and its affiliates to collect, use and disclose your personal data for the purposes set out in the Privacy Policy available at https://www.persolsingapore.com/policies. You acknowledge that you have read, understood, and agree with the Privacy Policy.
