Total 3 job vacancies by Brightecs Innovation Pte. Ltd.

Key Responsibilities:

• Responsible for the architecture design, RTL encoding (Verilog/SystemVerilog), and functional verification of digital control logic in 3D-NAND memory;
• Design a state machine (FSM) to manage complex NAND operation processes (such as Program, Read, Erase, Copy-back, Suspend/Resume, etc.);
• Develop a command decoder and address/parameter parsing logic to ensure compliance with JEDEC and internal specifications;
• Implement high-precision timing control logic to accurately generate the internal timing signals required for various operations (such as tR, tPROG, tBERS, etc.);
• Deeply involved in the physical layer and link layer logic implementation of ONFI (Open NAND Flash Interface) or Toggle Mode interface protocols, supporting DDR, NV-DDR, NV-LPDDR, and other modes;
• Collaborate with the analog/mixed-signal team to define array access timing, voltage switching windows, and read/write path control interfaces;
• Collaborate with firmware (FW) and system architecture teams to develop register maps, interrupt mechanisms, error handling strategies, and debug interfaces;
• Support UVM verification environment setup, provide Design for Testability (DFT) support, and participate in FPGA prototyping;
• Participate in chip bring-up, post-silicon debugging, and performance optimization to ensure products meet specification requirements.

Required Qualifications:

1. Education: Master's degree or above
2. Major: Microelectronics and Integrated Circuits, Electrical Engineering, Computer Engineering, or related fields;
3. Other Requirements:

• Minimum 5 years digital IC design experience, experience in NAND Flash or SSD controller projects is a plus;
• In-depth understanding of ONFI 4.x or Toggle 2.0/3.0 protocol specifications, with practical interface IP development or integration experience;
• Experience in control logic design under 3D-NAND or TLC/QLC architectures is a plus;
• Familiar with ECC control interfaces (such as LDPC/BCH engine scheduling and interaction);
• Excellent cross-functional collaboration skills, able to communicate efficiently with simulation, firmware, verification, testing, and product teams to jointly develop technical solutions.
• Experience with successfully tape-out and mass-produced memory chip projects is a plus.

Key Responsibilities:

• Lead the architecture design (e.g. memory cells, select transistors, and peripheral devices), process integration, electrical characterization, modeling and simulation, failure analysis for 3D NAND devices.
• Design and execute DoE, analyze the impact of process variations on device performance and reliability (such as durability and data retention), and propose improvement solutions.
• Collaborate with the process development team to assess new device architectures, driving technology iteration.
• Write detailed technical reports and support customers or internal teams in resolving related technical issues.

Required Qualifications:

1. Education: Master's degree or above
2. Major: Microelectronics, physics, material science & engineering, chemistry;
3. Other Requirements:

• 8+ years of semiconductor device work experience, 3+ years of 3D NAND work experience.
• In-depth knowledge of 3D NAND device physics, familiar with its principles, failure modes, and reliability mechanisms.
• Troubleshooting, and problem-solving capabilities, with experience in successfully improving device performance or yield.
• Familiar with advanced semiconductor manufacturing processes and integration flows.
• Strong cross-team communication and collaboration skills.

Key Responsibilities:

• Responsible for the performance, power consumption, and reliability testing and analysis of NAND memory products, and formulating test specifications and verification processes.
• Develop and maintain test equipment (ATE), including the definition and implementation of test modes such as BIST, DFT, and DFM, continuously improving test coverage and optimizing test time.
• Locate the causes of product failures after delivery and at the wafer stage through electrical failure analysis, design circuit analysis, physical failure analysis, and data analysis.
• Collaborate with the product design team and process team to identify the root causes of failures and drive the implementation of solutions.
• Support the testing and debugging of products in system-level applications (such as SSD, UFS, eMCP) to ensure efficient use by customers and the system side.
• Complete user manual verification, product test function verification, and participate in other test-related tasks assigned by the supervisor.

Required Qualifications:

1. Education and major: Master's degree or above in microelectronics, integrated circuits, electronic engineering, computer science, automation, physics, materials science, or other related STEM fields.

2. Experience requirements:

• Familiar with semiconductor product principles and testing mechanisms; background in memory (NOR/NAND Flash, SRAM, DRAM, phase-change memory, ferroelectric, etc.) testing or design verification is a plus.
• Experience in testing 3D-NAND, TLC/QLC, or flash memory products is a plus.
• Experience with successfully tape-out and mass-produced memory chip projects is a plus.

3. Technical skills:

• Proficient in C/C++, Python, Perl, etc., and familiar with UNIX/Linux environments.
• Experience in ATE (Automatic Test Equipment) development (e.g., T5830, T5833, Magnum V93K, etc.).
• Familiar with the functions, performance, and reliability indicators of memory products.
• Familiar with design-for-test (CFT), DFM, and other design-for-test (CFT) methodologies.

4. Other skills:

• Strong logical analysis, learning, and problem-solving abilities.
• Good communication, organizational, and teamwork skills.
• Proactive, steady, meticulous, responsible, and able to work under pressure.