Total 461 test engineer job vacancies in Art / Design / Entertainment category in The Philippines

This Lead Design Engineer will involve simulating and analyzing the signal integrity and power integrity of optical transceivers using various simulation tools. The Lead Design Engineer would be responsible for verifying the transceiver's performance, identifying potential problems, and developing solutions. The Lead Design Engineer would also work closely with other engineers to ensure that the transceiver meets all requirements.

Essential Duties and Responsibilities:

• Simulate and analyze signal integrity (SI) and power integrity (PI) of optical transceivers.

• Utilize simulation software to model and analyze transmission lines, connectors, and other components.

• Identify potential SI/PI issues, such as reflections, crosstalk, and noise.

• Develop and implement solutions to address SI/PI problems.

• Collaborate with other engineers to ensure the transceiver meets all performance requirements.

• Document and report simulation results.

Job Qualifications and Knowledge Requirements:

• Strong understanding of SI/PI principles and theories.

• Experience with SI/PI simulation software (e.g., HFSS, ANSYS).

• Experience with 3D/2D electromagnetic (EM) simulation tools.

• Familiarity with transmission line theory.

• Knowledge of optical transceiver design and operation.

• Experience with high-speed electronics and photonics.

• Strong analytical and problem-solving skills.

• Excellent communication and collaboration skills.

Education and Experience Requirements:

• Master's degree or higher in Electrical Engineering, Physics, or a related field.

• Relevant experience in SI/PI simulation and analysis.

• Experience with high-speed data transmission and fiber optics.

• Familiarity with test and measurement equipment (e.g., VNA, TDR).

• Lead project electrical phases: feasibility, detailed design, procurement, onsite construction supervision, and commissioning handover.

• Responsibilities will include Utility Power Applications, negotiating, updating and ensure contract obligations with Utility Authority.

• Design and validate power systems: switchgear, transformers, UPS, generators, PDUs, earthing, lighting, and EPMS/DCIM systems.

• Conduct load assessments, short-circuit studies, voltage drop and cable sizing. Generate single-line diagrams, equipment specs, and technical reports.

• Supervise site installations; perform inspections to ensure conformance with approved design, safety codes, and project schedule.

• Develop and oversee complex commissioning and functional testing procedures—include performance and failure-mode tests, pre-functional checklists, and comprehensive Cx reports.

• Manage Consultant and Architect through RFIs, change orders, submittals, progress reports, documentation control, and proper turnover protocols.

• Serve as liaison between client, contractors, vendors, and consultants; ensure electrical works meet design intent and contractual obligations.

• Monitor energy efficiency goals and recommend optimizations in alignment with sustainability targets.

• Assist in site commissioning training and handover to operations teams, supporting operations readiness

Requirements:

• Bachelor’s degree in Electrical Engineering or related field; relevant additional experience may substitute.

• 5+ years of electrical engineering experience, with at least 3–5 years in data center or mission-critical construction roles.

• Preferably, has experience the entire build cycle of data center facility in country such as Malaysia or Thailand.

• Proficient in design, modeling & drafting tools: AutoCAD, Revit, ETAP, Bluebeam, and similar software.

• Strong technical knowledge — UPS, switchgear, generators, EPMS/DCIM, load studies, and grounding systems.

• Capable communicator, able to drive coordination across stakeholders and lead site-based operations meetings with clarity.

• Certifications: Professional Engineer (BEM Malaysia), PMP, or other recognized credentials.

• Experience with BIM-based design and MEPF coordination in data center projects.

• Familiarity with standards: TIA 942, Uptime Institute tier certifications, IEC, local Malaysian codes.

• Prior knowledge of energy-efficient strategies or green data center deployments in Malaysia or Thailand.

Job Description

• Industry/ Organization Type: Manufacturing
• Position Title: Design Engineer (Construction)
• Working Location: Tuas
• Working Hours: 5 days (Mon – Fri, 8.00am – 5.30pm)
• Salary Package: Basic salary up to $4,500 + AWS + Variable Bonus
• Duration: Permanent Role

Key Responsibilities

• Carry out detailed analysis and design of civil and structural parts for various projects
• Work with other teams to develop effective and practical design solutions
• Prepare technical drawings, reports, and specifications to support project work
• Ensure all designs follow relevant codes, regulations, and safety standards
• Provide support on site during construction and help solve any issues that arise

APPLY NOW!!!

• Bachelor’s degree in Civil or Structural Engineering, or relevant discipline
• 5 years of experience in specialist building works
• Skilled in engineering design software such as ETABS, SAP2000, SAADPRO, and AutoCAD
• Knowledge of Singapore’s structural codes and regulations

Kindly apply through ANY of the following methods:

• Submit your application by clicking the APPLY button;
• Email your resume to Job@anradus.com.sg. Please indicate #76727 on the email subject.

Anradus Application Policy: We value each application and ensure every resume is reviewed. Our process is efficient, typically concluding within 3 working days. If you do not receive communication from us within this timeframe, it's likely that your application has not been shortlisted by our client. In such cases, we recommend continuing your job search to maximize your opportunities.

Anradus Pte Ltd | EA License No. 20C0161 | Angel Lim | EA Reg No.: R1769781

Description:

• You would be part of a dynamic digital SoC design team that develops state-of-the-art video processing, neural processing, advanced video analytics accelerators, and the entire Camera Processor SoC. You would be joining the team to explore, evaluate and define innovative design SoC architectures, to meet or exceed the technical requirements of the SoC. You would be responsible for the successful implementation of the designs in Verilog/SystemVerilog coding, metrics measurement to meet key objectives & results, and follow-through in comprehensive verifications to successful silicon.

Requirements:

• Experience in SoC architecture and design, and RTL coding with Verilog/SystemVerilog
• Experience in ARM or RISC-V processor system
• Experience in embedded C and assembly code programming
• Experience in analysis of power, timing and area
• Experience in at least one of scripting languages (e.g. Perl, Python, TCL, or Bash)
• Disciplined, quality-minded, and highly driven for excellence
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience
• Experience in always-on system, automotive system, secured system, bus interconnect, neural processing, video processing and video analytics is a plus
• Experience in system modelling and simulation using emulator and SystemC is a plus
• Experience in UVM verification methodology is a plus
• Passionate and strong in general programming is a plus

Job Description:

- Perform Civil, Structural Analysis and Design (entry-level) to meet project specifications

- Coordination and Liaise with Clients, Authority and Other Consultants, Contractors on Projects

- Ensuring Good Project Documentation and Submission to Authority and Clients

- Attend Project Meeting and Perform Inspections on Designed Works

- Reporting to Senior Engineer

Job Requirements:

- Candidate must possess at least a Bachelor's Degree / Post-Graduate Diploma / Professional Degree in Engineering (Civil/ Structural) or equivalent, recognized by Professional Engineering Board of Singapore

- At least 1 Year (s) of working experience in the related field is required for this position

- Good Working Attitude, Self-Motivated, Positive Thinking, Independent, Discipline, Attention to Details and Ownership of Tasks

- Familiar with Local Design Standard and Code

- Knowledge of Design Software, e.g., STAAD Pro, Plaxis, AutoCAD will be added advantage

- Candidate with longer experience or qualifications will be considered for Senior Positions

Key Responsibilities Key Responsibilities

RTL Design and Verification

• Develop synthesizable RTL in Verilog/SystemVerilog for custom on-chip test, monitoring, and diagnostic IP targeting analog and mixed-signal failure detection.
• Design and verify digital logic blocks such as test controllers, sequencing logic, sensor/interface control logic, measurement and monitoring logic, data capture and comparison logic, and failure detection and reporting logic.
• Build clean register and bus-connected interfaces, for example APB, AHB, or AXI-lite based control and status paths, to enable firmware interaction and subsystem integration.
• Develop testbenches, assertions, checkers, and block or subsystem-level verification environments to validate controller behavior, detection logic, configuration programming, fault response, and status reporting.
• Plan and execute functional verification for normal, corner, negative, and fault-injection scenarios, with adequate coverage of critical diagnostic behaviors.
• Collaborate with analog and mixed-signal designers to create or use behavioral models, stubs, and interface abstractions for realistic verification of failure mechanisms and observability paths.
• Debug RTL and simulation issues through waveform analysis, assertion-based checks, root-cause investigation, and close interaction with integration and product teams.
• Ensure the RTL is modular, reusable, timing-aware, synthesis-friendly, and scalable for integration across multiple SoC derivatives.

SoC Integration

• Integrate custom DFT / diagnostic IP into SoC subsystems and system-level test architecture with proper consideration for clock/reset structure, interrupt handling, and status visibility.
• Work closely with SoC integration and DFT teams to ensure compatibility with system test infrastructure, production test flows, diagnostic mechanisms, and firmware control requirements.
• Support integration readiness by addressing CDC, reset interactions, timing considerations, low-power implications, and implementation handoff requirements.

Cross-Functional Collaboration

• Work closely with digital, analog, and mixed-signal design teams, DFT engineers, SoC architects, and product/test engineering teams throughout the design and validation cycle.
• Translate analog or mixed-signal failure modes into robust digital detection logic suitable for on-chip test, screening, and diagnosis.
• Contribute to technical discussions on architecture tradeoffs, observability strategy, and practical silicon debug readiness.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, with 5–7 years of relevant experience.
• Strong hands-on experience in RTL design using Verilog/SystemVerilog.
• Practical experience in RTL verification, simulation, and debugging methodologies.
• Solid understanding of ASIC / SoC design flow including coding, simulation, synthesis, and integration.
• Good foundation in digital design concepts such as FSM design, datapath design, bus protocols (AXI/AHB/APB), clock-domain handling, reset strategy, and timing considerations.
• Experience working in complex SoC environments with cross-functional teams.

Preferred Qualifications

• Experience developing control, monitoring, or diagnostic IP associated with analog or mixed-signal subsystems.
• Exposure to behavioral modeling or interface definition for analog and mixed-signal verification use cases.
• Familiarity with subsystem-level integration, production screening considerations, and silicon debug support.
• Working knowledge of scripting or automation for verification, regression, or design productivity is an advantage.

Design Engineer (Civil & Structural) - LTA Project

Industry: A1 Main Contractor - Korean MNC

Office is near Jurong East MRT, Singapore

5.5 Days Alternate Saturday, 8am-6pm / 8am-12pm

Salary: $3,500 - $6,000 + Bonus

• Summary: We are seeking an experienced Design Engineer (Civil & Structural) to support major LTA MRT projects, work closely with the Design Manager and project teams to ensure timely, accurate, and compliant design throughout the project lifecycle.

Requirements

• Degree in Civil Engineering or related discipline.
• Minimum 5 years of engineering experience.
• At least 3 years of experience in civil & structural or architectural design for LTA MRT projects.

Job Description

• Assist the Design Manager and oversee the overall progress of design works on site.
• Manage drawing submission schedules in line with planned construction progress.
• Coordinate and review all design matters with LTA, authorities, consultants, and subcontractors.
• Provide technical solutions and offer design advice to internal teams.
• Manage and control design deliverables related to BIM, Technical, contractual, and cost requirements.
• Review subcontractors' shop drawings to ensure compliance with the design specifications and project standards.

Interested applicants can also send your resume to WA:+65 83472904 (Mr Samuel) and allow our Consultant to match you with our Clients.

No Charges will be incurred by Candidates for any service rendered.

Samuel Siaw

The Supreme HR Advisory Pte Ltd

EA No: 14C7279

Reg No: R2412474

Responsibilities

1. Develop design requirements for an NPU based on system-level specifications.
2. Being part of modelling the performance of the NPU module and its data transaction throughput.
3. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU.
4. Understanding the mathematics of different convolution operators including different arithmetic formats (fixed point and floating point)
5. Estimate, measure and optimize PPA (Performance / Power / Area) to meet key objectives and results.
6. Optimizing micro-architecture design for low power and area is required.
7. Work closely with verification engineers to ensure comprehensive testing and debug any issues.
8. Support integration into the overall system, conducting design checks, and addressing lint/timing/CDC issues.
9. Collaborate with software teams to assist in compiler and toolchain development and their debugging.
10. Produce clear and concise design documentation.

Requirements

1. 5+ years of digital design with at least 2 to 3 years of SoC design experience is preferred.
2. At least one cycle of NPU design completion experience is required.
3. Hands on experience in digital design is a must.
4. Experience in microarchitecture design, and RTL coding with Verilog/ System-Verilog.
5. Experience in synthesis, with analysis of power, timing and area.
6. Disciplined, quality-minded, and highly driven for excellence.
7. Excellent team player and good communication skills.
8. MSEE/BSEE in Electrical Engineering or Computer Engineering.
9. Understanding of convolution operator and number system is required.
10. Candidates with relevant experiences would be offered as Senior, taking on higher responsibilities.
11. Experience in UVM verification methodology is a plus.
12. A plus to have SoC design experience.
13. Experience with optimizing micro-architectures for low-power and low-area is a plus.
14. Knowledge in deep learning algorithms such as CNN / Transformer is a plus.
15. Experience with past design experience with NPU / GPU / DSP design is a plus.
16. Experience with ARM or RISC-V processor systems is a plus.
17. Passionate and strong in general programming is a plus.

Responsibilities

• Perform product design, prepare production drawing and must have sound knowledge of CNC programming.
• To schedule and plan all the orders including doors, locks and other products to meet project delivery schedule stipulated by the Projects and Sales Dept.
• To plan, forecast, optimize and organize various resources and provide technical support for the site installation work to achieve the quality and efficency for te project.
• To review and maintain quality assurance processes, in-process till finished product and installation quality control.
• To review and make improvement to product designs, process flows and QA/QC procedures, upkeep all quality manuals and SOPs, including reviewing productivity and efficiency of line and production of design and cutting drawings.
• To review periodically with the QC/QA engineer of the OEM to ensure that production are complying with the company quality standard.
• To assist in other business activities as and when assigned.

Requirements

• Candidate must possess at least Diploma/Advanced/Higher/Graduate Diploma, Bachelor's Degree/Post Graduate Diploma/Professional Degree in Mechanical Engineering.
• At least 5 Years of working experience in the related field of sheet metal products and fabrication.
• Proficient in 3D Modeling and AutoCAD.
• Proficient in SolidWorks.
• Experienced in design and calculation for Sheet metal products is a must for this position.

Leadtop Technology Pte Ltd is a chip design company based in Singapore. The Company has strong R&D capabilities and the core technical team members all have numerous years of experience in the semiconductor industry. We have rich industry experience and deep practical accumulation in IC design and business management.

Job Description:

1. Works with the front-end design team to complete the chip floorplan , clock architecture, and powerplan .

2. Takes charge of the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tapeout.

Position Requirements:

1. Holds a bachelor's degree or above in electronic engineering, microelectronics, or computer science.

2. At least 2 years of work experience in the digital backend design field. Tapeout experience at advanced technology is preferred.

3. Those with experience in TCL , Perl or Python script development and familiar with EDA tool design will be a plus.

4. Strong communication ability, good confidence and self-motivation, good teamwork spirit.

5. Salary is negotiable for excellent candidates.

Responsibilities:

1. Develop design requirements for an NPU based on system-level specifications.
2. Being part of modelling the performance of the NPU module and its data transaction throughput.
3. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU.
4. Understanding the mathematics of different convolution operators including different arithmetic formats (fixed point and floating point)
5. Estimate, measure and optimize PPA (Performance / Power / Area) to meet key objectives and results.
6. Optimizing micro-architecture design for low power and area is required.
7. Work closely with verification engineers to ensure comprehensive testing and debug any issues.
8. Support integration into the overall system, conducting design checks, and addressing lint/timing/CDC issues.
9. Collaborate with software teams to assist in compiler and toolchain development and their debugging.
10. Produce clear and concise design documentation.

Requirements

1. 8+ years of digital design with at least 2 to 3 years of SoC design experience is preferred.
2. At least one cycle of NPU design completion experience is required.
3. Hands on experience in digital design is a must.
4. Preferably has lead a team of at least 3 to 4 people in the past at the capacity of a design lead.
5. Experience in microarchitecture design, and RTL coding with Verilog/ System-Verilog.
6. Experience in synthesis, with analysis of power, timing and area.
7. Disciplined, quality-minded, and highly driven for excellence.
8. Excellent team player and good communication skills.
9. MSEE/BSEE in Electrical Engineering or Computer Engineering.
10. Understanding of convolution operator and number system is required.
11. Candidates with relevant experiences would be offered as Senior, taking on higher responsibilities.
12. Experience in UVM verification methodology is a plus.
13. A plus to have SoC design experience.
14. Experience with optimizing micro-architectures for low-power and low-area is a plus.
15. Knowledge in deep learning algorithms such as CNN / Transformer is a plus.
16. Experience with past design experience with NPU / GPU / DSP design is a plus.
17. Experience with ARM or RISC-V processor systems is a plus.
18. Passionate and strong in general programming is a plus.

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team

Requirements

• Minimum MSEE, or BSEE, or equivalent, plus 3+ years of Digital Design and verification related experience
• Experience / knowledge in CMOS Image Sensor and Image Signal Processing (ISP)
• Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.
• Strong debugging and problem-solving skills
• Good communication and interpersonal skills
• Results oriented and adaptable to changes

Job Description:

- Perform Civil, Structural Analysis and Design to meet project specifications

- Coordination and Liaise with Clients, Authority and Other Consultants, Contractors on Projects

- Ensuring Good Project Documentation and Submission to Authority and Clients

- Attend Project Meeting and Perform Inspections on Designed Works

- To Lead and Mentor Junior Engineer in Performing Engineering Task

- Reporting to Principal Engineer / Management

Job Requirements:

- Candidate must possess at least a Master's Degree /Bachelor's Degree / Post-Graduate Diploma / Professional Degree in Engineering (Civil/ Structural) or equivalent, recognized by Professional Engineering Board of Singapore

- At least 4 Year (s) of working experience in the related field is required for this position

- Good Working Attitude, Self-Motivated, Positive Thinking, Independent, Discipline, Attention to Details and Ownership of Tasks

- Familiar with Local Design Standard and Code

- Knowledge of Design Software, e.g., STAAD Pro, Plaxis, AutoCAD will be added advantage

• Design and develop automation and semiconductor equipment modules, optimizing performance, yield, and manufacturability using Design of Experiments (DOE).
• Lead the product development lifecycle from concept, design, and prototyping through validation and transition to high-volume manufacturing.
• Collaborate with Engineering, Integration, Modules, and cross-functional teams to troubleshoot technical challenges and ensure alignment throughout project execution.
• Ensure designs are manufacturing-ready, supporting integration into production with a focus on scalability, reliability, and cost efficiency.
• Define performance metrics, monitor development progress, and prepare technical reports and documentation for continuous improvement.

Requirements:

• Degree in Mechanical/Mechatronics Engineering or equivalent
• At least 3 years of experience in automation or semiconductor equipment design, with knowledge of high-precision machine design.
• Proficient in 3D CAD software and capable of producing detailed mechanical drawings with GD&T understanding.
• Strong problem-solving skills with the ability to collaborate across teams and support manufacturing integration.

If you are keen to apply for the position, kindly email your detailed resume in MS Word to hr@recruit-expert.com

Please note that only shortlisted candidates will be notified.

For more job opportunities, please visit our website at www.recruit-expert.com

EA Licence: 19C9701
Registration: R21100996

Leadtop Technology Pte Ltd is a chip design company based in Singapore. The Company has strong R&D capabilities and the core technical team members all have numerous years of experience in the semiconductor industry. We have rich industry experience and deep practical accumulation in IC design and business management.

Job Description:

1. Works with the front-end design team to complete the chip floorplan , clock architecture, and powerplan .

2. Takes charge of the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tapeout.

3.Researches the physical design methodology of advanced process nodes, and improvise the automatic physical design platform.

Position Requirements:

1. Holds a bachelor's degree or above in electronic engineering, microelectronics, or computer science.

2. At least 5 years of work experience in the digital backend design field. Hands-on project experience is required. Tapeout experience at advanced technology is preferred.

3. Those with experience in TCL , Perl or Python script development and familiar with EDA tool design will be a plus.

4. Strong communication ability, good confidence and self-motivated, good teamwork spirit.

5. Salary is negotiable for excellent candidates.