Total 10 process development engineer job vacancies in Art / Design / Entertainment category in bengaluru

Staff Engineer, Digital Design role requiring 8+ years of experience of Digital design in Analog Mixed signal ICs for developing Power Management ICs as part of 2.6B$ Power Business Unit at Renesas. Primary responsibilities include leading team which will fully own defining the microarchitecture to developing all Digital components of power management ICs, starting from System requirements. Due to the complex nature of Chips and significant Analog as well as Digital contents, collaboration with cross-functional teams to ensure successful integration of Digital and Analog components in ICs, is a must. The candidate will work on a wide range of exciting and cutting edge PMICs, including Linear and Switching DC-DC converters powering the next generation of most sought-after phones and handheld devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.

Essential Functions:

• Must have experience of defining Dig-Ana boundary and Digital design scope for Power Management ICs/Analog intensive ICs
• Must have experience of defining the micro-architectures and sub-blocks for the ICs to ensure optimized Digital design, RTL design and Gate level netlist etc.
• Must be aware of Power Sensitive digital design and doing Power estimation for the Digital I/Ps
• Must be able to handle Clock Domain Crossing across multiple clock domains seamlessly and in a glitch free manner.
• Should have experience of OTP, MTP, Efuse read/writes, controller design and data bus handling, Register read/write, Trimming of Analog parts/functions etc.
• Should be able to create Sequences (including Power UP/Down) and State Machines and Transitions to/from any state to another based on the IC requirements.
• Should be an expert of one or more Power Chip Communication I/Ps and protocols e.g. I2C, PMBUS, SVI3, SVID etc.
• Should be able to implement and analyse filters & feedback loops in Digital, conversant with Z-domain analysis.
• Must have done multiple silicon debugs, root cause analysis of issues, design to silicon correlation etc.
• Should understand commonly used control loop architectures (Constant Freq, Constant ON/OFF Time, Current mode etc) and pros/limitations of each.
• Must be able to bring in innovative ideas to improve designs to meet challenging specifications and achieve better system performance.
• Should be able to setup Digital design flows and methodologies including checklists, reviews to ensure quality designs and take them all the way to Silicon success.

Looking for a 5+ years experienced Engineer with good understanding of Analog concepts, experience of from scratch design of key analog blocks, integrating smaller blocks to create functional I/Ps and full ownership of those, ICs and well versed with Transistor level design flow, to join the 2.6B$ Power Business Unit. The candidate will get to work on a wide range of exciting products such as PMICs, Linear and Switching DC-DC converters powering the next generation of most sought-after phones and hand held devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.

Essential Functions:

• Must be proficient in designing and owning key analog blocks including Bangdap references, Analog Buffers, Op-Amps, Comparators, High speed level shifters etc.
• Must be able to come up with architectures to meet block level performance specifications.
• Must be well versed of the standard architectures and be able to bring in innovative ideas to improve designs to meet challenging specifications.
• Should have clear understanding of analog layouts and should be able to work closely with and guide layout engineers to ensure quality layout to meet the desired performance.
• Must be conversant with the standard design, extraction and simulation flows & tools, speed, convergence, accuracy trade-offs and should be able to optimize setups based on Pre/Post (with/without) Parasitic using simulator options, debug and navigate through tool related challenges.
• Should be able to mentor Freshers and Junior engineers for upscaling their technical skills as well as other skills needed for better efficacy.
• Should be able to develop multiple blocks with minimal supervision, take full ownership to drive all aspects within committed schedule and work closely with Sr members of Design team to support them build subsystem/chip top.
• Experience of silicon validation and debug is a strong advantage.
• Should have good understanding of ESD and be able to design the I/O ring for the IC

• We are seeking a Staff Engineer, who understand embedded NAND system design and firmware algorithms in order to create a test validation plans and implement them in modern object oriented languages.
• Work closely with the system architects and the firmware team to develop Validation plans, test bench and test cases
• Develop an overall validation strategy including defining validation infrastructure and validation methodology
• Debug the firmware and expose design issues
• Define and design functional tests required to meet customer needs
• Review SanDisk UFS/eMMC embedded NAND validation requirements and influence future SanDisk product design for debug and test
• Work with customers to understand field bugs and to enhance the validation coverage
• Interface with all key stakeholders to ensure product validation meets customer expectations and needs

Job Description: 

• Should be good in understanding the PCB board’s w.r.t layout schematics and information about the various active and passive components on the PCB.
• Good hands on BOM analysis and report preparation.
• Excellent debugging and Failure Analysis skills with exposure to tools like protocol analysers, Logical analysers, CRO etc. Should be good at reproducing and root causing the issues.
• Good Power analysis and Power tree Distribution Reverse engineering skills
• Good to have Experience in Storage Domain.
• Good to have Knowledge on the PCB Construction and Assembly details
• Good Experience in System level activities for hardware design and validation.
• Good to have Experience working with Flash memory technologies and internals.
• Good to have Experience in NVMe, SD/uSD, USB or PCIE protocols understanding.
• Mindset towards delivering the Highest Quality product to the customer.
• Must be execution focused, have zeal to learn more and do more. Take initiatives.
• Proven ability to achieve results in a fast moving, dynamic environment.
• Should be good team player, approachable with to do attitude.

Job Description: 

• Should be good in understanding the PCB board’s w.r.t layout schematics and information about the various active and passive components on the PCB.
• Good hands on BOM analysis and report preparation.
• Excellent debugging and Failure Analysis skills with exposure to tools like protocol analysers, Logical analysers, CRO etc. Should be good at reproducing and root causing the issues.
• Good Power analysis and Power tree Distribution Reverse engineering skills
• Good to have Experience in Storage Domain.
• Good to have Knowledge on the PCB Construction and Assembly details
• Good Experience in System level activities for hardware design and validation.
• Good to have Experience working with Flash memory technologies and internals.
• Good to have Experience in NVMe, SD/uSD, USB or PCIE protocols understanding.
• Mindset towards delivering the Highest Quality product to the customer.
• Must be execution focused, have zeal to learn more and do more. Take initiatives.
• Proven ability to achieve results in a fast moving, dynamic environment.
• Should be good team player, approachable with to do attitude.

Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.

We are seeking a highly motivated and innovative Staff IC Design Engineer (RTL Design) with strong experience in SoC development flows. In this role, you will play a pivotal part in the design and development of advanced integrated circuits that power Renesas MCU products. You will lead complex RTL design efforts, own key IP/subsystem deliverables, mentor junior engineers, and help evolve design methodologies and best practices.

Key Responsibilities

• Lead RTL design and development of complex IPs and subsystems within MCU SoCs, ensuring compliance with performance, power, and area (PPA) targets
• Drive micro-architecture definition and high-level digital design for assigned blocks
• Support SoC integration, delivering high-quality subsystem views and documentation to Back-end and Design Verification teams
• Own design quality checks, including lint, CDC, and RDC, and actively support functional verification of assigned blocks
• Collaborate closely with system architects, verification engineers, physical design teams, and software teams to define specifications and ensure seamless end-to-end integration
• Provide technical guidance and mentorship to junior engineers, raising overall team capability and design quality
• Contribute to continuous improvement of RTL design methodologies, coding guidelines, and design processes

Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.

Renesas India is seeking an experienced Staff / Senior Staff Physical Design Engineer to lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes. This role requires deep expertise in timing, congestion, power integrity, and clocking methodologies, along with strong cross-functional collaboration skills. While this role does not own SoC-level physical design, it plays a critical role in aligning subsystem implementation with overarching SoC strategies.

Key Responsibilities

• Lead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality
• Collaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements, without direct ownership of SoC-level execution
• Apply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture
• Develop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency
• Mentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption
• Work cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure
• Proactively identify, assess, and mitigate physical design risks, coordinating closely with SoC teams to manage impacts and drive solutions

Individual Contributor role for Technical leader with 2-5 years of experience in Analog and Power IC development within 2.6B$ Power Business Unit at Renesas. Primary responsibilities include leading the IP design blocks for development of power management ICs, including voltage regulators, power converters, and other related components and collaborate with cross-functional teams to ensure successful integration of ICs into larger systems. The candidate will work on a wide range of exciting and cutting edge PMICs, including Linear and Switching DC-DC converters powering the next generation of most sought-after phones and handheld devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio. This is an IC role with complete focus on product development and no people management.

Essential Functions:

· Identify and resolve technical challenges and risks.

· Should have a very good understanding of Power devices, operations and design trade-offs for better performance & reliability.

· Should be able to lead development and integration of complex I/Ps like +ve/-ve Charge Pumps, Source-Sink LDOs, Ultra-low power Oscillators (including Relaxation type), Temperature Sensor, Current Sense, SAR ADCs, House Keeping blocks, Protection (Thermal, Under-Voltage, Over-Voltage, Over Current etc) and other analog blocks including Bandgap references, V2I, Analog Buffers, Op-Amps, Comparators, High speed level shifters etc. Thorough understanding of Switch Cap circuits is a must.

· Must have in-depth understanding of and should be able to choose, design & compensate Control loops keeping in mind the target performance.

· Must be able to bring in innovative ideas to improve designs to meet challenging specifications and achieve better system performance.

· Should have in-depth knowledge of Analog layouts, FET layouts, Noise isolation techniques and be able to guide the layout development from floor planning till Chip Top completion and verification and do trade-offs based on desired performance.

· Must be conversant with the standard design, extraction and simulation flows & tools, speed, convergence, accuracy trade-offs and should be able to optimize setups based on Pre/Post (with/without) Parasitic using simulator options, debug and navigate through tool related challenges.

· Should be able to setup design flows and methodologies including checklists, reviews to ensure quality designs and take them all the way to Silicon success.

Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.

We are seeking a highly experienced IP Design Verification Engineer to join the Verification R&D team at Renesas. In this role, you will be a part of team responsible for SOC verification, ensuring first‑pass silicon success through building verification environment from scratch using best in class methodologies, metric‑driven verification, and intelligent coverage convergence using AI tools.

You will play a key technical role in defining verification strategies, architecting testbenches, defining Test Plans tracing Requirements, driving coverage closure using advanced automation and AI‑assisted techniques, and collaborating closely with Architecture, RTL, chip top, and Validation teams to deliver high‑quality, reusable IPs for next‑generation microcontrollers and microprocessors.

Responsibilities:

• Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off
• Define and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria
• Develop scalable, reusable UVM‑based verification environments for IP and subsystem verification
• Lead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metrics
• Apply AI/ML‑assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency
• Drive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verification
• Collaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration
• Review IP specifications and work with architects to translate requirements into robust verification plans and checkers
• Develop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors
• Work with EDA vendors to evaluate and adopt next‑generation verification, coverage, and analytics tools
• Mentor junior engineers and promote best‑in‑class verification practices and continuous improvement
• Support Gate‑Level Simulation (GLS), low‑power verification, and post‑silicon debug when required.
• Ensure IP deliverables meet quality, schedule, and reusability expectations for SoC integration.

Job Responsibilities: 

• Layout high performance Analog and Mixed Signal circuits using the latest Cadence Design Suite  

• Perform IP level layout tasks including device placement, routing, matching techniques, shielding, guard rings, and parasitic-aware layout practices.  

• Work at multiple levels of hierarchy, from macro level (block level) to Top-level (ESD/Pad frame) 

• Verify connectivity and design rules with Assura, Calibre, PVS 

• Use QRC extraction to analyze and reduce noisy/sensitive coupling 

• Use third party tools to analyze IR drops and p2p resistance 

• Liaise closely with analog designers on specific circuit requirements, e.g. power, matching, sensitivity, latch-up, ESD, etc. 

• Work with CAD and CAE engineers to improve processes or features