Total 23 process development engineer job vacancies in Art / Design / Entertainment category in Pasir Gudang

Job Description:

• Perform AUTOCAD 2D drawing - single line drawing, system general arrangement, system dimension details, system layout arrangement, system termination details and system internal wiring details;
• Work closely with the system engineer to gather the specifications and supplier documentations to proceed with the required drawings.
• Convert sketch from system engineer into technical drawings.

Requirements:

1. Diploma in telecom, or equivalent technical discipline.

2. AUTOCAD trained / certified

3. Proven 1 years’ experience in a similar role within the market/industry.

4. Well organized documentation and design standard

5. Objective driven, time-sensitive and resourceful.

6. Good to have System knowledge of PAGA, CCTV, GMDSS and related telecom systems;

7. Sound coverage study using CadnaA software will be a plus.

We are looking for an AutoCAD Draftsman to prepare, schedule, coordinate and monitor the projects that are being assigned to him/ her. Reporting to the Technology Director in the Energy Team, he/she will

Responsibilities:

• Work closely with the system engineer(s) to gather the specifications and supplier documentations to proceed with the required drawings. Experience with electrical drawings preferred.
• Convert sketch from system engineer(s) into technical drawings.
• Perform AutoCAD drawing for Equipment Dimension, Block Diagram, Wiring Diagram for telecommunication and security equipment.
• Familiar with 2D diagrams and line drawings.
• Manage projects submission to ensure timely submission for project tender and projects implementation.
• Any other ad hoc tasks related to business needs.

Requirements:

• Proficient with Auto CAD
• Experience in Marine, Oil and Gas Industry

My Client:

My client is a global technology company focused on advanced semiconductor and high-performance computing systems. The engineering team is dedicated to building next-generation ASIC solutions across advanced process nodes, supporting large-scale compute-intensive applications.The team operates in a highly technical and fast-paced environment, with strong emphasis on physical implementation, performance optimization, and full-chip delivery. They are currently expanding their physical design team to support growing project demands across advanced nodes.

Job Responsibilities:

• Perform end-to-end physical design implementation from netlist to GDSII for advanced ASIC projects.
• Work on key stages including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and optimization.
• Drive timing closure across MMMC scenarios, including setup/hold fixing, clock optimization, and ECO implementation.
• Conduct physical verification and signoff tasks (DRC, LVS, IR drop, EM analysis) to ensure tape-out readiness.
• Optimize power, performance, and area (PPA) through iterative design improvements.
• Collaborate closely with front-end design, DFT, and signoff teams to resolve integration and late-stage issues.
• Contribute to design methodology improvements and automation through scripting and tooling enhancements.

Job Requirements:

• Bachelor’s degree or above in Microelectronics, Electronic Engineering, or related fields.
• Understanding of physical design flow and IC development process.
• Familiarity with PnR tools such as ICC2, Fusion Compiler, or Innovus.
• Knowledge of timing analysis, power optimization, and physical verification concepts.
• Basic scripting skills (TCL / Python / Shell) for automation is a plus.
• Strong learning ability and willingness to work in advanced technology environments.

What They Offer:

• Opportunity to work on cutting-edge semiconductor projects at advanced technology nodes.
• Exposure to full-chip design flow and large-scale ASIC development.
• Competitive compensation and long-term growth opportunities.

About Us

Dada Consultants was established in 2017, with the commitment of providing the best recruitment services in Singapore. We are comprised of a dynamic head-hunting team dedicated to sourcing for highly competent professionals in IT industry. We provide enterprises with customized talent solutions, and bring talents to career advancement.

If it sounds like your next move, please don’t hesitate to apply. Kindly note that only shortlisted candidates will be contacted. Appreciate your understanding. Data provided is for recruitment purposes only.

www.dadaconsultants.com

EA Registration Number: R2197058

Business Registration Number: 201735941W. Licence Number: 18S9037

Leadtop Technology Pte Ltd is a chip design company based in Singapore. The Company has strong R&D capabilities and the core technical team members all have numerous years of experience in the semiconductor industry. We have rich industry experience and deep practical accumulation in IC design and business management.

Job Description:

1. Works with the front-end design team to complete the chip floorplan , clock architecture, and powerplan .

2. Takes charge of the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tapeout.

Position Requirements:

1. Holds a bachelor's degree or above in electronic engineering, microelectronics, or computer science.

2. At least 2 years of work experience in the digital backend design field. Tapeout experience at advanced technology is preferred.

3. Those with experience in TCL , Perl or Python script development and familiar with EDA tool design will be a plus.

4. Strong communication ability, good confidence and self-motivation, good teamwork spirit.

5. Salary is negotiable for excellent candidates.

Leadtop Technology Pte Ltd is a chip design company based in Singapore. The Company has strong R&D capabilities and the core technical team members all have numerous years of experience in the semiconductor industry. We have rich industry experience and deep practical accumulation in IC design and business management.

Job Description:

1. Works with the front-end design team to complete the chip floorplan , clock architecture, and powerplan .

2. Takes charge of the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tapeout.

3.Researches the physical design methodology of advanced process nodes, and improvise the automatic physical design platform.

Position Requirements:

1. Holds a bachelor's degree or above in electronic engineering, microelectronics, or computer science.

2. At least 5 years of work experience in the digital backend design field. Hands-on project experience is required. Tapeout experience at advanced technology is preferred.

3. Those with experience in TCL , Perl or Python script development and familiar with EDA tool design will be a plus.

4. Strong communication ability, good confidence and self-motivated, good teamwork spirit.

5. Salary is negotiable for excellent candidates.

Process Associate Scientist I – Viral Clearance
1 year contract potential to renew

Company Description:
Our client is an in Healthcare, Life Science, and Electronics company. They are across the globe with innovating science and technology solutions to enrich people’s lives. Together, they dream big and are passionate about caring for our rich mix of people, customers, patients, and planet.

Your role:
As Process Associate Scientist I – Viral Clearance (VC) you will be part of the Contract Testing Services team that designs and delivers Viral Clearance validation studies for biopharmaceutical companies across the APAC region. In this role you will perform a variety of Good Manufacturing Practice (GMP) / Good Laboratory Practice (GLP) operations and conduct client processes for Viral Clearance studies. You will maintain the process laboratories and equipment in the validated state and conduct client studies with appropriate regulatory compliance under the oversight of the Study Director, independently performing Virus Reduction Filtration (VRF) and execute chromatographic process under supervision of more senior process associate scientists. As part of your daily responsibilities, you may support investigations of events and improvement projects. The Process Associate Scientist I will work closely with the rest of process team, study management, Lab Study Coordinating (LSC) team and end-point testing team to execute client studies on time and right first time.

The post holder will be able to perform the following functions.

Brief role description:

• Works within the Viral Clearance laboratories following Standard Operating Procedures (SOPs) and relevant compliance regulations.
• May prepare high quality VRF (nanofiltration) workbooks.
• Independently performs client scale-down virus nanofiltration operations, and work closely with VRF vendor to ensure VRF process is completed according to schedule.
• Execution of client’s scale-down chromatographic processes under supervision of more senior process associate scientists.
• Works closely together with study management team, lab study coordinating (LSC) team, end-point testing team, Quality and project managers to ensure client studies are completed on time, to the appropriate scientific and regulatory standards.
• Accurately and promptly records data to meet appropriate scientific and GLP/GMP regulatory standards.
• May support in investigations of study deviations/laboratory events as required.
• Housekeeping of labs: performs weekly/monthly cleanings/inventory/housekeeping. Ensure that consumables needed in the client labs are available throughout the week (when studies are on-going).
• To support Point Of Contact (POC) of each client lab in all activities that pertain to general daily housekeeping & maintenance of the labs.
• Ensures equipment in labs are maintained in the validated state with timely implementation of periodic maintenance and calibration.
• Ensures a safe and healthy work environment at all times by not only complying with but actively embracing health and safety policies and procedures, ensuring the safety of yourself and others within the workplace.
• May support in writing/revising Standard Operating Procedures (SOPs) and workbooks.
• Supports lab projects impacting routine operations.

BioReliance (Process Solution Services)

• May need to support other VC teams in carrying out various lab activities which can include Spiking, Collection, Reads and Computing etc.

The above list of job duties is not exclusive or exhaustive and the post holder will be required to undertake such tasks as may reasonably be expected within the scope of the post.

Requirements

• Min Degree in any Science field with minimum 1 year of related experience
• Computer literacy and entry of data into databases (LIMS, ELN, SAP, etc.)
• Ability to complete documentation (both handwritten and electronic) neatly and accurately

Interested parties, please click on APPLY button. Alternatively, you can share your CV at joleyn.chin@randstadsourceright.com.sg

EA License: 94C3609
Reg No: R1440247

About Company

Founded in 2022, XG Tech is driving the future of smart vehicles. Its mission is to empower the digital transformation of automobiles, moving from distributed computing to a centralized, cross-domain platform.

XG Tech focuses on the intelligent cockpit—the next frontier of differentiation—while seamlessly integrating advanced driving systems. By reimagining cars as mobile living spaces, XG Tech aligns with the evolving trend of vehicles becoming the “third living space.”

Role Summary

As an IC Design Engineer, you will develop and implement micro-architectures and RTL designs for complex digital IPs and SoCs. You will work across the full ASIC flow, from RTL coding to synthesis, timing closure, and validation, ensuring high-quality, efficient, and reliable designs.

Key Responsibilities

• Develop and implement micro-architecture for complex digital blocks.
• Write synthesizable RTL code in Verilog/SystemVerilog for various IPs and SoCs.
• Perform linting, CDC (Clock Domain Crossing), and low-power checks (UPF/CPF).
• Conduct logic synthesis, timing constraints generation, and timing closure support.
• Collaborate with verification engineers to define test plans and ensure design quality.
• Support pre-silicon validation and post-silicon bring-up and debug activities.
• Create and maintain technical documentation.

How you will stand out

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related field.
• Proven experience in ASIC design flow and methodologies.
• Strong proficiency in RTL coding using Verilog or SystemVerilog.
• Hands-on experience with synthesis, timing analysis, and scripting languages (e.g., TCL, Python).
• Knowledge of low-power design techniques and power integrity issues is a plus.
• Familiarity with industry-standard EDA tools from Synopsys, Cadence, or Siemens.
• Excellent problem-solving skills and a strong team-oriented mindset.
• Effective communication skills and the ability to work in a dynamic, global team environment.

XG Tech is committed to providing equal employment opportunities by country, state, and local laws. XG Tech does not discriminate against employees or applicants based on conditions such as race, color, gender identity and/or expression, sexual orientation, marital and/or parental status, religion, political opinion, nationality, ethnic background or social origin, social status, disability, age, indigenous status, and union.

About Company：

Founded in 2022, XG Tech is driving the future of smart vehicles. Its mission is to empower the digital transformation of automobiles, moving from distributed computing to a centralized, cross-domain platform.

XG Tech focuses on the intelligent cockpit—the next frontier of differentiation—while seamlessly integrating advanced driving systems. By reimagining cars as mobile living spaces, XG Tech aligns with the evolving trend of vehicles becoming the “third living space.”

Role Summary

As a SoC/Chip Architect, you will define and drive the architecture of next-generation semiconductor products. You will require a broad technical understanding to deliver optimal, high-performance designs, balancing performance, power, area, and cost.

Key Responsibilities

• Work with product management, marketing, and customers to define product requirements and specifications.
• Perform high-level modeling and analysis to explore architectural trade-offs and define optimal micro-architectures.
• Develop detailed architecture specifications for SoCs, CPUs, GPUs, or other complex IPs.
• Provide technical guidance and leadership to design and verification teams throughout the product development cycle.
• Research and evaluate emerging technologies and industry trends.
• Collaborate with software, system, and hardware teams to ensure a cohesive system architecture.
• Author and present technical documents and proposals to stakeholders.

Qualifications and Skills:

• Master’s or PhD degree in Electrical/Electronics Engineering, Computer Engineering, or a related field.
• Significant proven experience in chip architecture, micro-architecture, or a senior design role.
• Deep understanding of computer architecture concepts (e.g., CPUs, GPUs, memory hierarchies, interconnects, coherency).
• Experience with performance modeling and analysis tools.
• Strong knowledge of software and hardware interactions.
• Proficiency in scripting languages (e.g., Python, C++) for modeling and analysis.
• Excellent leadership, communication, and presentation skills.
• Ability to think creatively and solve complex, multi-dimensional problems.

XG Tech is committed to providing equal employment opportunities by country, state, and local laws. XG Tech does not discriminate against employees or applicants based on conditions such as race, color, gender identity and/or expression, sexual orientation, marital and/or parental status, religion, political opinion, nationality, ethnic background or social origin, social status, disability, age, indigenous status, and union.

Job Responsibilities

1. Responsible for the design, simulation, and verification of analog circuits

2. Perform layout floor plan simulations and ensure optimization

3. Collaborate with layout engineers to finalize circuit design work

4. Prepare comprehensive design documentation and maintain detailed records throughout project lifecycle

5. Coordinate with application, product, and test engineers to ensure successful mass production of the product

Job Requirements

1. Bachelor's degree or above in Microelectronics, Electronic Engineering, Communication Engineering, or related fields

2. Solid foundational knowledge in analog circuit design principles

3. Hands-on experience in designing one or more of the following circuits: LDO, Oscillator, IO, ESD, ADC, DAC, PLL, and filters

4. Proficiency in at least one programming language such as Python, MATLAB, or C

5. Strong problem-solving skills and good communication and learning abilities.

6. Passion for analog circuit design, with a strong interest in advancing knowledge and skills in this field

KEY RESPONSIBILITIES:

• Contribute to IP selection and architecture definition; create functional specifications.
• Perform PPA evaluation and optimization.Develop RTL for functional blocks/units with architectural features and timing constraints, targeting synthesis and APR.
• Support debugging across RTL simulation, gate-level, and post-layout simulations.
• Conduct quality checks using FE EDA tools such as Spyglass.lint, CDC, RDC, etc.
• Take ownership of the full project lifecycle, from architecture to production.

PREFERRED EXPERIENCE:

• > 10 years of hands-on experience in digital frontend design.
• Strong proficiency in Verilog/VHDL.
• Hands-on experience with logic FE tools (e.g., VCS, Verdi, Spyglass, DC).
• Experience in Static Timing Analysis is a strong plus.
• Prefer candidates with experience implementing advanced-process chips.
• Familiarity with low-power design and power simulation preferred.
• Proficiency in TCL, Perl, or similar scripting languages is a plus.
• Prior experience with multiple tape-outs and chip bring-up is preferred.
• Leadership or management experience is an advantage.

ACADEMIC CREDENTIALS:

• Bachelor or Masters Degree in Electronic Engineering, with years relevant work experience.

Job Description

• Lead and perform tasks in RTL synthesis, floor planning, placement, clock tree synthesis, routing, and physical verification.
• Manage signoff activities including Static Timing Analysis (STA), EMIR, and Physical Verification (PV) to ensure tape out-quality designs.
• Collaborate with cross-functional teams (DFT, RTL, STA, Packaging) to drive seamless integration and execution.
• Plan, monitor, and execute project execution, set deadlines, track milestones, and report progress to leadership.
• Guide, mentor, and develop the team, fostering technical excellence and a collaborative environment.
• Troubleshoot and resolve design challenges, proactively communicating risks and mitigation strategies.
• Interface with EDA vendors and keep up-to-date with industry trends, tools, and methodologies.
• Prepare and deliver technical presentations, document processes, and contribute to organizational knowledge base.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering.
• Hands-on experience in physical design, including synthesis, PNR, STA, EMIR, and PV is a plus.
• Strong expertise with EDA tools: Synopsys, Cadence, or Siemens (e.g., Design Compiler, IC Compiler, Fusion Compiler, Genus, Innovus, PrimeTime, Voltus, Calibre).
• Proven track record of successful tapeouts for complex semiconductor products.
• Solid understanding of power, performance, area (PPA) optimization techniques.
• Excellent project management skills, including resource planning, task tracking, and team leadership.
• Strong communication and interpersonal skills; ability to present technical material and interact confidently with cross-functional teams.
• Experience leading and mentoring engineers.
• Familiarity with advanced process nodes (3nm, 2nm)

Interested candidates may apply through the application system. Shortlisted candidates will be notified.

PERSOL Singapore Pte Ltd • RCB No.200007268E EA License No. 01C4394 • EA Registration No. R23111944 (Loh Hui Ru Clara)

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Job Description:

• Responsible for cutting edge technology node’s SRAM compiler design and deliver best quality of design kit.
• Seamlessly collaborate with SRAM design and layout team to achieve highest quality of design kit delivery.
• Responsible for data analysis and platform development of memory usage big data.
• Responsible for physical verification (DRC/ERC/LVS/ANT/PERC) on SRAM compiler.
• Responsible for spice simulation on timing, power and noise on SRAM compiler.
• Responsible for QA check and development on SRAM compiler.

Job Requirements:

• Bachelor or Master Degree in Electrical and Electronic Engineering or Computer Engineering or Computer Science.
• Multi-task capability and strong self-driven characteristics to meet challenging schedule.
• Proficient  with  Perl,  Shell,  Python,  C/C++  languages,  knowledge  with  AI  machine  learning algorithm and infrastructure is an added advantage.
• Strong interpersonal skills to work with team members with multi-cultural environment
• Knowledge of high performance, low power SRAM/ROM and VLSI design is an added advantage. Experience with EDA tools will be helpful.
• Candidate with experience is preferable.

PERSOL Singapore PteLtd • UEN No. 200007268E • EA License No. 01C4394 •EA Registration No.R22109454 (Malcolm Lee Jun Hao)

By sending us your personal data andcurriculum vitae (CV), you are deemed to consent to PERSOL Singapore Pte Ltdand its affiliates to collect, use and disclose your personal data for thepurposes set out in the Privacy Policy available at https://www.persolsingapore.com/policies. You acknowledge that you have read, understood, andagree with the Privacy Policy.

The primary role of Engineering function within Product Development team is to create specifications and designs for new products or improvements and enhancements to existing products. Works closely with customers, developers and other stakeholders to understand and define customer needs in these designs. Features are aligned to a timetable and areas of responsibility. Developers may solicit customers for feedback regarding product usability and desired future enhancements. Software Engineers who design, write and test code for the product should be matched in the either Software Engineering Applications or Systems. Product developers who specialize in hardware systems should be matched to Hardware Engineering.

Let’s talk about Responsibilities

• The primary objective of Design Engineering specialization within Engineering (PD) Job Family is the research, design and development of thoughtful products that solve complex problems through an innovative and thorough approach to product development.

• Key responsibilities include integrating ideas that take into account the needs of our customers, usability, therapy, technology trends, intellectual property, environmental factors and design for high volume manufacturing; Building relationships that foster passion for design and delivery of ground breaking products; Understanding people and producing thoughtful products that make their lives better

• Performs work in a specialized area of expertise that requires knowledge of fundamental themes, principles and concepts. Typically requires a university degree or equivalent work experience.

• Responsibilities might include:
  
  (1) Performing routine professional-based activities (early in career)
  
  (2) Contributing to and managing projects (mid-career)
  
  (3) Providing advice/direction in primary areas of expertise (specialist and expert)
  
  (4) Leveraging professional expertise and relationships to contribute to strategy and drive business results (principal)relationships to contribute to strategy and drive business results (principal)

• Networks with contacts outside own area of expertise.

• Leads a cooperative effort among members of a project team.

• Works independently, with guidance in only the most complex situations.

• Frequently leads sub-functional teams or projects and train and mentor junior team members.

• Serves as a best practice resource within own area of work.

Let’s talk about Qualifications and Experience

Required:

Preferred:

• Bachelor’s degree.

• Minimum of 2 years of related experience.

• Applies functional knowledge and existing methodologies to solve complex problems or execute specialized projects.

• Exercises judgment in selecting methods, techniques and evaluation criteria for obtaining results.

• Determines methods and procedures on new assignments.

Responsibilities

• Responsible for algorithms and logic design and verification related to ASIC/AI/CPU chips under advanced processes
• Responsible for chip testability design and related work
• Responsible for maintaining the IC development environment and tool processes for chips, as well as designing In-House EDA tools

▌ Requirements

• Bachelor's degree or higher in fields including but not limited to Mathematics, Physics, Electronic Science and Technology, Microelectronics, Information and Communication Engineering, Computer Science and Technology, or Materials Science and Engineering
• Understanding of the IC development process, with a certain theoretical foundation in digital circuits, practical skills, and innovation ability

Regret to inform that only shortlisted candidates will be notified.
www.dadaconsultants.com
EA Registration Number: R1878287
Business Registration Number: 201735941W.

Job Description:

• Support the technical team and construction team for all design matters.
• Review all technical documentation and drawings of the Project works.
• Work closely with consultant on the scope of services, design and project deliverables to enhance site efficiency and constructability.
• Manage design approval process and coordination with the clients, consultants and subcontractors in a timely manner to resolve all technical issues.
• Ensure strict compliance of the design in accordance with contractual requirements.
• Identifies and highlight to management and project team of any potential risks or issues that will impact project performance.
• Support tender team and prepare technical tender documents as per specifications for bidding of civil and structural engineering projects as when assigned.

Job Requirement:

• PE Board Recognised Degree in Civil Engineering.
• Minimum 1 year of design management experience with at least 2 year of design experience in consultant firm.
• Strong coordination and collaboration with other disciplines.
• Good interpersonal and communication skills .
• Good organization and time management skills.