Total 640 design intern job vacancies in Art / Design / Entertainment category in The Philippines

Our esteemed client in the Construction industry is seeking an Architecture Design Coordinator to join their dynamic team:

• Employment Type: Permanent
• Position: Architecture Design Coordinator
• Location: Central
• Working Hours: 5 days, 8.30am to 5.30pm
• Salary Package: Up to $6,000 + Bonus

Job Responsibilities:

• Coordinate with a team of BIM Modellers to support design development and project coordination.
• Prepare and update construction-related drawings, including shop drawings for submission and approval.
• Liaise with consultants, subcontractors, and internal teams to track site progress and resolve technical issues.
• Assist in tender preparation and documentation.

Job Requirements:

• At least a Bachelor’s Degree in Architecture or a related field.
• Minimum 3 years of relevant experience with a main contractor, preferably in building or mixed-development projects.
• Proficient in reading and interpreting construction drawings.
• Comfortable working in a fast-paced environment.

Ready to apply? Here’s how: 

• Click the APPLY button, or 
• Email your resume (in MS Word or PDF format) to adelin@intuitrecruitment.com. Include the job title in your email subject line for prompt processing. 

Only shortlisted candidates will be notified. 

By submitting your application, you consent to the collection and use of your personal data under Personal Data Protection Act (PDPA). 

Adelin Chong | EA Personnel Reg No.: R1875641 

Intuit Recruitment Pte Ltd | EA License No.: 25C2793 

As a Design Verification Manager, you are expected to carry out the following responsibilities.

• Be in-charge of a passionate verification team that is constantly pushing the limits
• Developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification.
• Conduct thorough test plan reviews systematically and execute the plan on-time with high quality.
• Achieve zero-defect, with the best and smartest approach to the large verification space.

Requirements

• Strong knowledge of SoC design principles, including IP block integration and system-level verification
• Experience with test plan development, execution, and analysis
• Familiarity with EDA tools and development flows for ASIC verification
• Highly disciplined, quality-minded, and highly driven for excellence.
• Excellent team leader and good communication skills.
• Strong expertise in UVM verification methodology.
• Experience in C and/or a scripting language such as python or perl.
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with at least 10 years of relevant experience.
• Experience in RTL design is a plus.
• Experience in video processing and video analytics is a plus.
• Passionate and strong in general programming is a plus.

Description:

• You would be part of a dynamic digital SoC design team that develops state-of-the-art video processing, neural processing, advanced video analytics accelerators, and the entire Camera Processor SoC. You would be joining the team to explore, evaluate and define innovative design SoC architectures, to meet or exceed the technical requirements of the SoC. You would be responsible for the successful implementation of the designs in Verilog/SystemVerilog coding, metrics measurement to meet key objectives & results, and follow-through in comprehensive verifications to successful silicon.

Requirements:

• Experience in SoC architecture and design, and RTL coding with Verilog/SystemVerilog
• Experience in ARM or RISC-V processor system
• Experience in embedded C and assembly code programming
• Experience in analysis of power, timing and area
• Experience in at least one of scripting languages (e.g. Perl, Python, TCL, or Bash)
• Disciplined, quality-minded, and highly driven for excellence
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience
• Experience in always-on system, automotive system, secured system, bus interconnect, neural processing, video processing and video analytics is a plus
• Experience in system modelling and simulation using emulator and SystemC is a plus
• Experience in UVM verification methodology is a plus
• Passionate and strong in general programming is a plus

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team, ISP Design leaders in other sites, and Digital System Design Team
• Leading, supervising and mentoring a team of RTL design engineers

Requirements

• Minimum MSEE, or BSEE, or equivalent, plus 7+ years of Digital Design and verification related experience
• 3+ years project management / people management experience / skill
• Experience / knowledge in CMOS Image Sensor and image signal processing (ISP)
• Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.
• Ability to lead teams and collaborate effectively with people in different functions
• Strong time management skills to ensure timely completion of deliverables
• Good communication and interpersonal skills
• Results-oriented and adaptable to changes

Key Responsibilities Key Responsibilities

RTL Design and Verification

• Develop synthesizable RTL in Verilog/SystemVerilog for custom on-chip test, monitoring, and diagnostic IP targeting analog and mixed-signal failure detection.
• Design and verify digital logic blocks such as test controllers, sequencing logic, sensor/interface control logic, measurement and monitoring logic, data capture and comparison logic, and failure detection and reporting logic.
• Build clean register and bus-connected interfaces, for example APB, AHB, or AXI-lite based control and status paths, to enable firmware interaction and subsystem integration.
• Develop testbenches, assertions, checkers, and block or subsystem-level verification environments to validate controller behavior, detection logic, configuration programming, fault response, and status reporting.
• Plan and execute functional verification for normal, corner, negative, and fault-injection scenarios, with adequate coverage of critical diagnostic behaviors.
• Collaborate with analog and mixed-signal designers to create or use behavioral models, stubs, and interface abstractions for realistic verification of failure mechanisms and observability paths.
• Debug RTL and simulation issues through waveform analysis, assertion-based checks, root-cause investigation, and close interaction with integration and product teams.
• Ensure the RTL is modular, reusable, timing-aware, synthesis-friendly, and scalable for integration across multiple SoC derivatives.

SoC Integration

• Integrate custom DFT / diagnostic IP into SoC subsystems and system-level test architecture with proper consideration for clock/reset structure, interrupt handling, and status visibility.
• Work closely with SoC integration and DFT teams to ensure compatibility with system test infrastructure, production test flows, diagnostic mechanisms, and firmware control requirements.
• Support integration readiness by addressing CDC, reset interactions, timing considerations, low-power implications, and implementation handoff requirements.

Cross-Functional Collaboration

• Work closely with digital, analog, and mixed-signal design teams, DFT engineers, SoC architects, and product/test engineering teams throughout the design and validation cycle.
• Translate analog or mixed-signal failure modes into robust digital detection logic suitable for on-chip test, screening, and diagnosis.
• Contribute to technical discussions on architecture tradeoffs, observability strategy, and practical silicon debug readiness.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, with 5–7 years of relevant experience.
• Strong hands-on experience in RTL design using Verilog/SystemVerilog.
• Practical experience in RTL verification, simulation, and debugging methodologies.
• Solid understanding of ASIC / SoC design flow including coding, simulation, synthesis, and integration.
• Good foundation in digital design concepts such as FSM design, datapath design, bus protocols (AXI/AHB/APB), clock-domain handling, reset strategy, and timing considerations.
• Experience working in complex SoC environments with cross-functional teams.

Preferred Qualifications

• Experience developing control, monitoring, or diagnostic IP associated with analog or mixed-signal subsystems.
• Exposure to behavioral modeling or interface definition for analog and mixed-signal verification use cases.
• Familiarity with subsystem-level integration, production screening considerations, and silicon debug support.
• Working knowledge of scripting or automation for verification, regression, or design productivity is an advantage.

Responsibilities

1. Develop design requirements for an NPU based on system-level specifications.
2. Being part of modelling the performance of the NPU module and its data transaction throughput.
3. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU.
4. Understanding the mathematics of different convolution operators including different arithmetic formats (fixed point and floating point)
5. Estimate, measure and optimize PPA (Performance / Power / Area) to meet key objectives and results.
6. Optimizing micro-architecture design for low power and area is required.
7. Work closely with verification engineers to ensure comprehensive testing and debug any issues.
8. Support integration into the overall system, conducting design checks, and addressing lint/timing/CDC issues.
9. Collaborate with software teams to assist in compiler and toolchain development and their debugging.
10. Produce clear and concise design documentation.

Requirements

1. 5+ years of digital design with at least 2 to 3 years of SoC design experience is preferred.
2. At least one cycle of NPU design completion experience is required.
3. Hands on experience in digital design is a must.
4. Experience in microarchitecture design, and RTL coding with Verilog/ System-Verilog.
5. Experience in synthesis, with analysis of power, timing and area.
6. Disciplined, quality-minded, and highly driven for excellence.
7. Excellent team player and good communication skills.
8. MSEE/BSEE in Electrical Engineering or Computer Engineering.
9. Understanding of convolution operator and number system is required.
10. Candidates with relevant experiences would be offered as Senior, taking on higher responsibilities.
11. Experience in UVM verification methodology is a plus.
12. A plus to have SoC design experience.
13. Experience with optimizing micro-architectures for low-power and low-area is a plus.
14. Knowledge in deep learning algorithms such as CNN / Transformer is a plus.
15. Experience with past design experience with NPU / GPU / DSP design is a plus.
16. Experience with ARM or RISC-V processor systems is a plus.
17. Passionate and strong in general programming is a plus.

Job Description

• Industry/ Organization Type: Building and Construction
• Position Title: Design Manager (Facade / Building Envelope)
• Working Location: Redhill
• Working Hours: 5 Days (Mon - Fri, 8:30AM – 6PM)
• Salary Package: Basic Salary + AWS + Variable Bonus
• Duration: Permanent

Key Responsibilities

• Lead and manage the design team in executing façade design works according to project requirements and timelines.
• Plan, organize, and monitor design activities to ensure alignment with the overall construction schedule.
• Provide leadership and guidance to team members, including work allocation, design quality checks, and productivity improvement.
• Review and verify design drawings, cutting lists, and technical deliverables to ensure compliance with specifications and standards.
• Coordinate effectively with consultants, main contractors, and other stakeholders to resolve design and technical issues.
• Identify and report any additional work or variations to the Project or Contract Manager for approval.
• Support site teams in resolving design clashes and provide technical input during construction.
• Participate in design workshops and review meetings, ensuring constructability and design quality are maintained throughout the project.
• Manage design changes efficiently to minimize schedule disruptions and cost impacts.
• Address interface issues between disciplines during various design stages and ensure smooth communication across teams.
• Perform other ad-hoc duties as assigned.

APPLY NOW!!!

• Minimum 5 years of experience in façade design or related fields.
• Proficient in design development and design management processes.
• Knowledge of Revit and Rhino is an advantage; must be able to read and extract information from 3D models in these formats.

Kindly apply through ANY of the following methods:

• Submit your application by clicking the APPLY button;
• Email your resume to Job@anradus.com.sg. Please indicate #79467 on the email subject.

Anradus Application Policy: We value each application and ensure every resume is reviewed. Our process is efficient, typically concluding within 3 working days. If you do not receive communication from us within this timeframe, it's likely that your application has not been shortlisted by our client. In such cases, we recommend continuing your job search to maximize your opportunities.

Anradus Pte Ltd | EA License No. 20C0161 | Angel Lim | EA Reg No.: R1769781

Responsibilities:

1. Develop design requirements for an NPU based on system-level specifications.
2. Being part of modelling the performance of the NPU module and its data transaction throughput.
3. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU.
4. Understanding the mathematics of different convolution operators including different arithmetic formats (fixed point and floating point)
5. Estimate, measure and optimize PPA (Performance / Power / Area) to meet key objectives and results.
6. Optimizing micro-architecture design for low power and area is required.
7. Work closely with verification engineers to ensure comprehensive testing and debug any issues.
8. Support integration into the overall system, conducting design checks, and addressing lint/timing/CDC issues.
9. Collaborate with software teams to assist in compiler and toolchain development and their debugging.
10. Produce clear and concise design documentation.

Requirements

1. 8+ years of digital design with at least 2 to 3 years of SoC design experience is preferred.
2. At least one cycle of NPU design completion experience is required.
3. Hands on experience in digital design is a must.
4. Preferably has lead a team of at least 3 to 4 people in the past at the capacity of a design lead.
5. Experience in microarchitecture design, and RTL coding with Verilog/ System-Verilog.
6. Experience in synthesis, with analysis of power, timing and area.
7. Disciplined, quality-minded, and highly driven for excellence.
8. Excellent team player and good communication skills.
9. MSEE/BSEE in Electrical Engineering or Computer Engineering.
10. Understanding of convolution operator and number system is required.
11. Candidates with relevant experiences would be offered as Senior, taking on higher responsibilities.
12. Experience in UVM verification methodology is a plus.
13. A plus to have SoC design experience.
14. Experience with optimizing micro-architectures for low-power and low-area is a plus.
15. Knowledge in deep learning algorithms such as CNN / Transformer is a plus.
16. Experience with past design experience with NPU / GPU / DSP design is a plus.
17. Experience with ARM or RISC-V processor systems is a plus.
18. Passionate and strong in general programming is a plus.

Position Overview:

• As a design verification engineer, you will be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space.

Requirements:

• Experience in UVM verification methodology
• Disciplined, quality-minded, and highly driven for excellence,
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience, but are open to fresh graduates with outstanding results
• Candidates with relevant experiences would be offered as Senior or Staff, taking on higher responsibilities
• Experience in video processing and video analytics is a plus
• Passionate and strong in general programming is a plus

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team

Requirements

• Minimum MSEE, or BSEE, or equivalent, plus 3+ years of Digital Design and verification related experience
• Experience / knowledge in CMOS Image Sensor and Image Signal Processing (ISP)
• Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.
• Strong debugging and problem-solving skills
• Good communication and interpersonal skills
• Results oriented and adaptable to changes

Description:

• You would be part of a dynamic digital SoC design team that develops state-of-the-art video processing, neural processing, advanced video analytics accelerators, and the entire Camera Processor SoC. You would be joining the team to explore, evaluate and define innovative design SoC architectures, to meet or exceed the technical requirements of the SoC. You would be responsible for the successful implementation of the designs in Verilog/SystemVerilog coding, metrics measurement to meet key objectives & results, and follow-through in comprehensive verifications to successful silicon.

Requirements:

• Experience in SoC architecture and design, and RTL coding with Verilog/SystemVerilog
• Experience in ARM or RISC-V processor system
• Experience in embedded C and assembly code programming
• Experience in analysis of power, timing and area
• Experience in at least one of scripting languages (e.g. Perl, Python, TCL, or Bash)
• Disciplined, quality-minded, and highly driven for excellence
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience
• Experience in always-on system, automotive system, secured system, bus interconnect, neural processing, video processing and video analytics is a plus
• Experience in system modelling and simulation using emulator and SystemC is a plus
• Experience in UVM verification methodology is a plus
• Passionate and strong in general programming is a plus

Position Overview:

• As a design verification engineer, you will be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space.

Requirements:

• Experience in UVM verification methodology
• Disciplined, quality-minded, and highly driven for excellence,
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience, but are open to fresh graduates with outstanding results
• Candidates with relevant experiences would be offered as Staff or Sr. Staff, taking on higher responsibilities
• Experience in video processing and video analytics is a plus
• Passionate and strong in general programming is a plus

Part time intern needed to do on site survey.

must commit minimum 2 to 4 weeks

working hours: 830am to 6pm.

Working days: 5 days per week.

Committement: Not needed

salary: $1200 to 1500 per month

Do not need any experience as we will train you

Kindly whatsapp Jay at 87928898 / wa.me/6587928898

Kindly whatsapp Jay at 87928898 / wa.me/6587928898

Role Overview 

Hands-on 6 months sales internship embedded with the APJ Sales & Marketing team. You'll work on real pipelines, real prospects, and real commercial targets from Day 1 — not a research-only role. 

What is there for you?

• Work directly alongside senior sales & technology leaders 

• Real exposure to AI-powered enterprise deals

• Contribute to pipelines spanning APJ, Middle East & the US 

• Flat org structure — direct executive access, no back-office roles 

• Own a territory, prospect list & outcomes from Day 1 

Key Responsibilities 

• Lead Research: Profile target accounts using LinkedIn Sales Navigator & ZoomInfo 

• Outbound Outreach: Draft & execute email, LinkedIn, and phone outreach sequences 

• Pipeline Qualification: Qualify leads through discovery calls; log activity in Salesforce CRM 

• CRM & Reporting: Maintain prospect records; generate weekly pipeline reports for APJ leadership 

• Market Intelligence: Track industry trends across BFSI, manufacturing, tech & retail verticals 

• Marketing Collaboration: Align outbound campaigns with demand generation programs & regional events 

• Sales Enablement: Prepare decks, collateral & competitive positioning materials 

Core Competencies 

• Commercial curiosity & business acumen 

• Strong written & verbal communication (C-suite audience) 

• Research, synthesis & analytical thinking 

• Resilience & persistence in a high-rejection sales environment 

• Salesforce CRM, LinkedIn Sales Navigator, MS Office / Google Workspace 

• Team player across a distributed global setup (SG, India, US) 

Who Should Apply 

• Background in Business, Marketing, or Technology preferred 

• Prior sales, BizDev or customer-facing experience is a plus — not mandatory 

• Comfortable with cold outreach to senior executives 

• English fluency required; Mandarin or Bahasa is an advantage to communicate with regional customers.
  

  CEI No: R2093683 / EA No: 07C3147

Senior Design Engineer

• Working Location: Jurong East

• Working Days: Monday - Friday

• Working Hours: 8:30am - 5:15pm

• Salary range: SGD 5,500 to SGD 8,000 monthly, 13th month, SGD 250 transport allowance

Basic Functions

Specialize in customization on electrical design work related to diesel generator sets, synchronizing system, switchgears, controllers and associated equipment. Design drawings, BOM for factory production fabricating. Preparing documentation for approval. Integration with other equipment industry, such as generators protection, switchgears, BMS, etc.

Specific Responsibilities

1. Design & produce electrical drawings, BOM and documentation for factory production

2. Understands the ISO standards and various regions standards for design considerations

3. Works closely with procurement to engage and qualify suppliers and parts

4. Works closely with manufacturing team in the electrical installations of the product and ensures smooth flow in the production line

5. Have good understanding of generator controller and alternator working concepts

6. Works closely with Industrial Solutions and sales to understand the design requirements and provide timely response to tender submission

7. Support in testing and validation of design including parameter optimization for controllers, governors, AVR, PLCs, HMI 

8. Design & Program various controllers, PLCs, HMI if necessary

9. Provides on-site and remote troubleshooting support if needed

10. Lead in continuous improvement projects to reduce costs and improve work efficiency

11. Assists in managing, training, developing and mentoring junior engineers, ensure standard engineering practice among the engineers

Qualifications / Requirements

• Degree in Electrical Engineering with 7-8 years of relevant experience; or

• Diploma in Electrical Engineering with 10-12 years of relevant experience

• Required to be skilled in SEE Electrical.

• Experience in process change management tools and methodologies

• Specialized skills or subject matter expert in electrical related field will be an advantage 

• Knowledge in PLC electrical design, controllers, generators, switchgears and transformers

LIEW ONN KEE REG NO : R22108518

THE SUPREME HR ADVISORY EA NO:14C7279