Total 4 Senior Executive front end developer job vacancies in Manufacturing / Production category

As Front End Central Product Integration Engineer-Chip Package Interaction at Micron Technology, Inc., you will be responsible for working with global Micron network to drive each silicon node's Packaging Product yield, quality improvement, new product introduction (NPI) through technical expertise, business process management and project execution.

In addition, you will be responsible in integrating solutions by connecting cross-functional expertise, standardizing the business process and regularly benchmarking internal and external intelligence to achieve the highest value bits and productivity. 

Responsibilities and Tasks

• Promote worldwide synergy for improved benchmark performance and efficiency gains through global project management and execution, network BKM leveraging and enhancement, and business process creation and re-engineering.

• Define strategies to ensure that Packaging Technology and interaction with Front End manufacturing process are fully developed and qualified well ahead of any qualification of the product itself.  

• Lead the PI Loop taskforce and/or team in network to address yield and quality challenges, optimize process flow in a timely manner to achieve BIC yield performance.

• Maintain and enhance domain knowledge and technical expertise, explore innovation opportunities with strategic thinking and systematic approach.

• Maintain a strong and open relationship with peer group and managers in other functional areas within central team and outside in areas such as Fab, TD, Product Engineering, GQ. Communicate and respond to issues in a timely manner. Help drive to fix the issue where necessary.

• Demonstrate ability to give effective presentations to both small and large groups on project updates and new initiative proposals.

• Periodically follow up with manager to ensure all type of goals are met and get assistance to remove obstacles.

• Travel to Micron Fab locations as necessary for face-to-face work.

Requirements

• Bachelor’s  or Master's degree in Electrical Engineering, Microelectronics, Physics, Chemistry, Material Science Engineering or related field

• A minimum of 2 years of experience in Back-End-of-Line (BEOL) semiconductor processing or process integration is required

• Must be willing to travel as needed to support departmental goals, with an expected travel frequency of approximately 20–50%

• Knowledge in Semiconductor Device Physics, DRAM operations, wafer fabrication process flows, parametric/electrical test and probe yield.

• The experience on DRAM HPM, BEOL integration, advanced packaging and layout will be a plus to this job position.

• Good data analysis, troubleshoot, problem solving, reporting and presentation skills with a strong attention to detail.

• Good multi-tasking, verbal, and written communication skills.

• Strong interpersonal skills and customer/co-worker relationships. Successfully demonstrated teamwork skills with a strong focus on developing good team dynamics.

• Good organizational capabilities and ability to work effectively with minimal supervision.

• Intermediate to advanced PC skills including Microsoft Office.

• Ability to be flexible with job responsibilities and take the initiative to assume added responsibilities.
  

  Maximizes yield by working on tools, the process, or wafer fabrication recipes. Troubleshoots wafer fabrication problems and performs root cause analysis. Works with other process areas to understand and control process deviations. Long-term investigation of defect issues may require extensive work with shift engineering and other functional areas. Evaluates products to ensure they meet the required design and performance specifications. Conducts research to assess process adjustment requirements and recommends process improvements or equipment changes needed to efficiently manufacture new product or part types.

Responsibilities and Tasks:

• Drive end‑to‑end front‑end process integration across multiple modules to support yield, functionality, and scalability

• Lead cross‑module root cause analysis for complex yield detractors and integration issues

• Support yield ramp, derivative matching, and node transitions through focused integration execution

• Act as a core cPIE contributor for assigned programs, partnering closely with site PI/PE/Device teams

• Develop and apply Best Known Methods (BKM) within owned integration scope

• Provide technical input to POR/TOR and ECN decisions affecting integration margin

• Apply data‑driven analysis to quantify process sensitivity, margin, and risk

• Participate in SWAT teams and technical deep dives for high‑impact issues

• Mentor junior engineers and contribute to knowledge sharing within CPIE

• Collaborate with PI, PE, Device, Yield, TD, and Quality to accelerate learning cycles

Required Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Chemical Engineering, Physics, or a related discipline

• At least 3 years of strong front‑end semiconductor manufacturing experience, with demonstrated exposure to process integration across multiple modules

• Proven ability to perform complex root‑cause analysis on yield, functionality, or integration issues using data‑driven methods

• Solid understanding of device–process interactions and system‑level integration trade‑offs

• Experience collaborating across PI, PE, Device, Yield, TD, and Quality organisations

• Ability to influence technical decisions through analysis, insight, and technical credibility

• Strong written and verbal communication skills for technical reviews, deep dives, and cross‑team alignment

Good to Have:

• Direct experience supporting advanced DRAM technology nodes and/or technology ramps

• Demonstrated ownership of integration loops, yield ramp activities, or derivative matching efforts

• Experience contributing to or developing Best Known Methods (BKM), standard practices, or reusable integration solutions

• Familiarity with POR/TOR definition, ECN review, and change risk assessment from an integration perspective

• Exposure to statistical analysis, yield modelling, or advanced analytics applied to manufacturing data

• Track record of leading or contributing to SWAT teams or high‑impact technical investigations

• Experience mentoring junior engineers or serving as a technical reference within a team
  

  Maximizes yield by working on tools, the process, or wafer fabrication recipes. Troubleshoots wafer fabrication problems and performs root cause analysis. Works with other process areas to understand and control process deviations. Long-term investigation of defect issues may require extensive work with shift engineering and other functional areas. Evaluates products to ensure they meet the required design and performance specifications. Conducts research to assess process adjustment requirements and recommends process improvements or equipment changes needed to efficiently manufacture new product or part types.

Responsibilities and Tasks:

• Drive end‑to‑end front‑end process integration across multiple modules to support yield, functionality, and scalability

• Lead cross‑module root cause analysis for complex yield detractors and integration issues

• Support yield ramp, derivative matching, and node transitions through focused integration execution

• Act as a core cPIE contributor for assigned programs, partnering closely with site PI/PE/Device teams

• Develop and apply Best Known Methods (BKM) within owned integration scope

• Provide technical input to POR/TOR and ECN decisions affecting integration margin

• Apply data‑driven analysis to quantify process sensitivity, margin, and risk

• Participate in SWAT teams and technical deep dives for high‑impact issues

• Mentor junior engineers and contribute to knowledge sharing within CPIE

• Collaborate with PI, PE, Device, Yield, TD, and Quality to accelerate learning cycles

Required Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Chemical Engineering, Physics, or a related discipline

• At least 3 years of strong front‑end semiconductor manufacturing experience, with demonstrated exposure to process integration across multiple modules

• Proven ability to perform complex root‑cause analysis on yield, functionality, or integration issues using data‑driven methods

• Solid understanding of device–process interactions and system‑level integration trade‑offs

• Experience collaborating across PI, PE, Device, Yield, TD, and Quality organisations

• Ability to influence technical decisions through analysis, insight, and technical credibility

• Strong written and verbal communication skills for technical reviews, deep dives, and cross‑team alignment
  

  Good to Have:

  • Direct experience supporting advanced DRAM technology nodes and/or technology ramps

  • Demonstrated ownership of integration loops, yield ramp activities, or derivative matching efforts

  • Experience contributing to or developing Best Known Methods (BKM), standard practices, or reusable integration solutions

  • Familiarity with POR/TOR definition, ECN review, and change risk assessment from an integration perspective

  • Exposure to statistical analysis, yield modelling, or advanced analytics applied to manufacturing data

  • Track record of leading or contributing to SWAT teams or high‑impact technical investigations

  • Experience mentoring junior engineers or serving as a technical reference within a team
    

    Maximizes yield by working on tools, the process, or wafer fabrication recipes. Troubleshoots wafer fabrication problems and performs root cause analysis. Works with other process areas to understand and control process deviations. Long-term investigation of defect issues may require extensive work with shift engineering and other functional areas. Evaluates products to ensure they meet the required design and performance specifications. Conducts research to assess process adjustment requirements and recommends process improvements or equipment changes needed to efficiently manufacture new product or part types.

Key Responsibilities

• Lead and drive global Product Integration initiatives to improve yield, quality, and benchmark performance across technology nodes and products.

• Centralize and synthesize project information (design requirements, test challenges, yield learning) from multiple global teams and drive execution to closure.

• Drive yield breakthroughs by understanding the end‑to‑end test flow, product design and operation, packaging interactions, and manufacturing processes while balancing yield vs. reliability requirements.

• Foster technical innovation by characterizing device failure modes using deep knowledge of device architecture, physics, packaging interaction, and available test/process knobs.

• Define and drive strategies to ensure Packaging Technology and Chip‑Package Interaction are developed and qualified ahead of product qualification.

• Lead cross‑functional and cross‑site taskforces (Product, Test, Yield, Design, Fab, Packaging, Quality, TD) to resolve yield and quality challenges in a timely manner.

• Promote network Best‑Known‑Method (BKM) development, standardization, and business process creation or re‑engineering to improve productivity and efficiency.

• Maintain strong working relationships with stakeholders in Fab, Technology Development, Product Engineering, Test Engineering, Quality, and Packaging teams.

• Communicate project status, risks, and proposals effectively through clear written reports and technical presentations.

• Proactively identify obstacles, escalate when needed, and partner with management to drive successful outcomes.

• Travel to Micron fab and development sites as needed to support project execution and alignment.
  

  Minimum Qualifications

  • Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Microelectronics, Physics, Chemistry, Materials Science Engineering, or a related field.

  • 2+ years of experience in one or more of the following:

  • Product Integration

  • Test Engineering

  • Yield Engineering

  • Design Engineering

  • BEOL semiconductor processing or process integration

  • Strong knowledge of Semiconductor Device Physics and DRAM product operations.

  • Understanding of wafer fabrication process flows, parametric/electrical testing, and probe yield.

  • Strong data analysis, debugging, troubleshooting, and problem‑solving skills with attention to detail.

  • Effective verbal and written communication skills with the ability to present to both small and large technical audiences.

  • Demonstrated ability to collaborate across functions and cultures, building strong customer and co‑worker relationships.

  • Ability to work independently with minimal supervision, manage multiple priorities, and stay organized.

  • Intermediate to advanced PC skills, including Microsoft Office.

  • Willingness to travel approximately 20–50% to support global project needs.

  • Flexibility to adapt to changing priorities and take on additional responsibilities as needed.

  Preferred Qualifications

  • Experience in DRAM High Bandwidth Memory (HBM) products.

  • Exposure to DRAM HPM, advanced packaging, chip‑package interaction, BEOL integration, or layout‑related topics.

  • Experience working across Test, Product, Yield, Design, Packaging, and Manufacturing organizations.

  • Proven ability to drive alignment and execution in central or network‑level roles.

  • Strong interest in innovation, continuous improvement, and scalable solution development.