Staff NAND/CMOS Device Engineer

Employer: Sandisk GK (Japan)

■Job Description
You will be responsible for product and technology development of 3D NAND.
Your primary role will be to electrically evaluate and analyze memory cells fabricated on development wafers produced in Yokkaichi, as well as the peripheral circuits and transistors that drive them. Based on these analyses, you will contribute to process development and drive technology development aimed at improving product performance and reliability.
You will collaborate with teams across domestic and international sites, including process, test, and design teams, sharing responsibilities and jointly advancing development.  

Cell Device:
-Evaluate next-generation flash memory, with a focus on optimizing cell array operating voltages and timing, as well as reliability evaluation
-Contribute to manufacturing process improvements based on cell array characterization results
-Perform statistical analysis of variability in mass production cell array characteristics
-Develop test programs for cell array characterization
-Develop screening tests to improve early failure (DPPM) rates
-Conduct failure analysis using electrical methods
-Collaborate with overseas sites on the above activities 
-Lead product steering toward commercialization

CMOS Device:
-Perform electrical evaluation and analysis of next-generation CMOS (transistors and passive devices)
-Design TEGs and define design rules for next-generation  CMOS development
-Improve CMOS characteristics toward mass production (reliability and variability improvements, etc.)
-Conduct electrical evaluation and statistical data analysis (e.g., using Spotfire) to improve yield related to CMOS
-Develop screening and stress tests to improve DPPM (customer and field failure rate)
-Serve as an interface between backend sites (overseas) and frontend fabs (domestic)