Total 11 job vacancies by Sandisk

We're looking for an experienced Senior Manager to lead our Memory Reliability & Qualification engineering organization in Bengaluru, India. In this strategic leadership role, you will oversee the complete NAND Flash memory qualification lifecycle, drive innovation, and build a high-performing engineering team. You will be responsible for translating business objectives into technical strategies while maintaining operational excellence and delivering world-class solutions.

• Lead and mentor a team of NAND Technology Reliability engineers, fostering a culture of innovation, collaboration, and continuous improvement
• The candidate should have a vast experience in semiconductor industry along with strong skills in Failure Analysis, Root Cause Analysis, Device Physics and programming
• Develop and execute memory qualification strategies aligned with organizational goals and business demands
• Oversee the complete qualification lifecycle, from requirements gathering through successful memory qualification, ensuring timely delivery and attention to details
• Manage engineering budgets, resource allocation, and project timelines to optimize operational efficiency
• Make critical technical decisions based on the performance and reliability checkpoint data to judge the memory technology
• Collaborate with cross-functional teams including product engineering, test engineering and product management to ensure seamless delivery
• Develop and implement performance metrics to track engineering team productivity and deliverables quality
• Represent the team in executive meetings and strategic planning sessions

• Providing technical leadership and expertise to define requirements for framework through programming/scripting of verification and emulation flows.
• Partnering with ASIC engineers to deploy and support framework for technologies like advanced verification environment configuration and management.
• Collaborating cross-functionally to optimize verification and emulation workflows and standardize methodologies.

• Need to work in collaboration with global analog teams across sites.
• Will be responsible for driving innovation in Analog IP designs.
• Responsible for design of IPs like Voltage regulators, LDO, Current and Voltage reference, High Voltage charge pumps, temperature sensors, oscillators etc using industry standard EDA tools.
• Should provide technical leadership and mentor junior engineers.
• Responsible for developing processes and robust design methodology.
• Help build overall competency in Analog domain.

Key Responsibilities – Mask Design Technologist

• Layout Design & Optimization: Develop and optimize peripheral and core circuit layouts for Analog, Digital, and Mixed-signal domains, ensuring adherence to design specifications, performance requirements, and foundry rules.

• Design Verification: Perform DRC (Design Rule Check) and LVS (Layout Versus Schematic) verification, parasitic extraction, and sign-off methodologies to guarantee design integrity and first-pass success.

• Power Distribution & Floorplanning: Analyze and implement full-chip power distribution strategies and floorplanning optimization to ensure efficient electrical performance, minimize parasitics, and reduce die size.

• Cross-Functional Collaboration: Work closely with design and process engineering teams across multiple sites to resolve issues, align methodologies, and drive project success while maintaining high standards of accuracy and consistency.

In this senior leadership role, you will lead the development of advanced mask layouts for next-generation memory technologies, strengthening our company’s position as a leader in the semiconductor industry.

In this position, the individual will be responsible for design & development of device FW for next-generation PCIe / NVMe SSD products.

Responsibilities:

• Design, implement, debug firmware for the next generation of SSDs
• HW Interface drivers, algorithm design and implementation
• Contribute to the SSD firmware and play a significant role in delivering next generation SSDs to market
• Design and implement firmware algorithms needed to achieve best in class performance goals
• Support failure analysis on test systems
• Active participation in technical design, implementation reviews across teams and functions

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Represents Package Engineering in cross-functional teams and ensures that packages are characterized, qualified, and introduced into production in a timely manner while meeting all mechanical, electrical, performance, reliability, and quality requirements.        
• Lead cross-functional teams, factories, and other engineers while managing the entire package life cycle process.          
• Works with the Packaging R&D teams worldwide to develop and qualify new and emerging packaging technology required to support business needs
• Support assembly yield improvement and package cost reduction programs.  
• Lead new product from low volume to high volume production transition with yield and quality meeting goals. Ensure FMEA, SOD, Control Plan, recipe guideline, SPC and other assembly controls are ready prior to high volume production.
• Work on innovative ideas for best-in-class package design.

Job Description: 

• Should be good in understanding the PCB board’s w.r.t layout schematics and information about the various active and passive components on the PCB.
• Good hands on BOM components, analysis and report preparation.
• Excellent equipment Failure Analysis skills to tools like protocol analysers, Logical analysers, CRO etc.
• Good to have Experience in Storage Domain products HW knowledge.
• Good to have Knowledge on the PCB Construction and Assembly details
• Mindset towards delivering the Highest Quality product to the customer.
• Must be execution focused, have zeal to learn more and do more. Take initiatives.
• Proven ability to achieve results in a fast moving, dynamic environment.
• Should be good team player, approachable with to do attitude.

Job Description: 

• Should be good in understanding the PCB board’s w.r.t layout schematics and information about the various active and passive components on the PCB.
• Good hands on BOM analysis and report preparation.
• Excellent debugging and Failure Analysis skills with exposure to tools like protocol analysers, Logical analysers, CRO etc. Should be good at reproducing and root causing the issues.
• Good Power analysis and Power tree Distribution Reverse engineering skills
• Good to have Experience in Storage Domain.
• Good to have Knowledge on the PCB Construction and Assembly details
• Good Experience in System level activities for hardware design and validation.
• Good to have Experience working with Flash memory technologies and internals.
• Good to have Experience in NVMe, SD/uSD, USB or PCIE protocols understanding.
• Mindset towards delivering the Highest Quality product to the customer.
• Must be execution focused, have zeal to learn more and do more. Take initiatives.
• Proven ability to achieve results in a fast moving, dynamic environment.
• Should be good team player, approachable with to do attitude.

Job Description: 

• Should be good in understanding the PCB board’s w.r.t layout schematics and information about the various active and passive components on the PCB.
• Good hands on BOM analysis and report preparation.
• Excellent debugging and Failure Analysis skills with exposure to tools like protocol analysers, Logical analysers, CRO etc. Should be good at reproducing and root causing the issues.
• Good Power analysis and Power tree Distribution Reverse engineering skills
• Good to have Experience in Storage Domain.
• Good to have Knowledge on the PCB Construction and Assembly details
• Good Experience in System level activities for hardware design and validation.
• Good to have Experience working with Flash memory technologies and internals.
• Good to have Experience in NVMe, SD/uSD, USB or PCIE protocols understanding.
• Mindset towards delivering the Highest Quality product to the customer.
• Must be execution focused, have zeal to learn more and do more. Take initiatives.
• Proven ability to achieve results in a fast moving, dynamic environment.
• Should be good team player, approachable with to do attitude.

Role Summary:

We are seeking a Software Engineer to contribute to the development of AI/ML software for our AI Privacy Box platform. This role involves implementing and optimizing LLM and RAG workflows, with a focus on efficient use of storage and system resources.

Key Responsibilities:

• Develop AI/ML software components for the AI Privacy Box platform.
• Implement and integrate LLM and RAG models into the software stack.
• Work on performance optimization of AI workloads using storage and system‑level techniques.
• Contribute to system software components interacting with OS, memory, and I/O subsystems.
• Collaborate with senior engineers on architecture, design, and optimization.
• Debug, test, and maintain high‑quality, production‑ready code.

Required Skills:

• Knowledge of Machine Learning and AI/ML fundamentals.
• Exposure to LLMs and RAG concepts or frameworks.
• Proficiency in C and/or C++.
• Understanding of Operating Systems concepts.
• Strong knowledge of Data Structures and Algorithms.

Role Summary:

We are seeking a Software Engineer to contribute to the development of AI/ML software for our AI Privacy Box platform. This role involves implementing and optimizing LLM and RAG workflows, with a focus on efficient use of storage and system resources.

Key Responsibilities:

• Develop AI/ML software components for the AI Privacy Box platform.
• Implement and integrate LLM and RAG models into the software stack.
• Work on performance optimization of AI workloads using storage and system‑level techniques.
• Contribute to system software components interacting with OS, memory, and I/O subsystems.
• Collaborate with senior engineers on architecture, design, and optimization.
• Debug, test, and maintain high‑quality, production‑ready code.

Required Skills:

• Knowledge of Machine Learning and AI/ML fundamentals.
• Exposure to LLMs and RAG concepts or frameworks.
• Proficiency in C and/or C++.
• Understanding of Operating Systems concepts.
• Strong knowledge of Data Structures and Algorithms.