Total 502 process development engineer job vacancies in Art / Design / Entertainment category in Australia

Responsibilities

• Design and implement digital logic for ASIC, AI, and CPU chip development using advanced process nodes to meet performance targets
• Develop and execute verification plans by performing simulation, debugging, and validating design functionality to ensure quality
• Implement design-for-testability (DFT) features to enhance chip test coverage and improve reliability
• Participate in RTL design, integration, and optimization to achieve performance, power, and area (PPA) goals
• Maintain and improve IC development environments, tool flows, and verification methodologies for efficient workflows
• Contribute to the development and optimization of in-house EDA tools and automation scripts to streamline design processes
• Collaborate effectively with cross-functional teams including architecture, physical design, and software to ensure successful tape-out

Preferred competencies and qualifications

• Knowledge of hardware description languages such as Verilog and SystemVerilog
• Exposure to ASIC/SoC design, AI chips, or high-performance computing environments

Requirements

• Bachelor’s degree or higher in Electrical Engineering, Computer Science, Microelectronics, Physics, or related fields
• Solid foundation in digital logic design and computer architecture demonstrated through academic or project work
• Familiarity with IC design flow including RTL design, simulation, and verification methodologies
• Strong analytical thinking and problem-solving skills applied in fast-paced learning environments
• Candidates with relevant academic background, including those at early stages of their career, are encouraged to apply.

Responsibilities:

• Lead RTL design, simulation, and verification for company ASIC/SoC products, ensuring robustness.
• Integrate and validate IP blocks for seamless system functionality.
• Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs.
• Collaborate with backend team in RTL coding, implementation, and synthesis for successful tapeout.
• Create and maintain reusable IPs for AI/in-memory computing.
• Support Post-Si testing to ensure product functionality and quality.
• Mentor junior engineers to facilitate their professional growth.
• Contribute to design reviews for improved product performance and reliability.
• Stay current on RTL design methodologies for efficiency and quality.
• Collaborate with cross-functional teams for successful product development.

Requirements:

• Minimum Master in Electrical Engineering with 5 years of working experience with emphasis on RTL/SoC/digital design.
• Proficient in Verilog and SystemVerilog.
• Proficient in VCS, Verdi, or similar industry-standard tools.
• Skilled in pre-layout and post-layout simulation.
• Knowledgeable about the design flow and collaboration with backend teams.
• Familiar with AMBA APB and AXI protocols.
• Familiar with RISC/Arm or other core architectures.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact win@hkmsvs.com for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Responsibilities:

• Implement simulation models of AI SoC or subsystem designs.
• Perform computer architecture performance simulation.
• Analyse experimental data and perform architecture explorations.
• Identify bottlenecks in design and provide feedback on micro-architecture.
• Propose chip architecture optimizations for chip performance, power, and area improvement.
• Cross-team collaborations to deliver high quality chip products.
• Validate the correctness of the AI chip designs.

Qualification：

• Master’s degree or above in Electrical & Electronic Engineering, Computer Science, or a related field.
• Familiarity with computer architecture concepts, such as AI accelerators, CPUs, Network-on-Chip (NoC), and memory hierarchy.
• Proficiency in C/C++ programming.
• Experience with computer architecture simulation is preferred.
• Strong learning ability, with good communication and collaboration skills.
• Bilingual in English and Mandarin is an advantage to support cross-regional collaboration with Mandarin-speaking stakeholders.
• Fresh graduates with relevant project or internship experience are encouraged to apply.

Key Responsibilities Key Responsibilities

RTL Design and Verification

• Develop synthesizable RTL in Verilog/SystemVerilog for custom on-chip test, monitoring, and diagnostic IP targeting analog and mixed-signal failure detection.
• Design and verify digital logic blocks such as test controllers, sequencing logic, sensor/interface control logic, measurement and monitoring logic, data capture and comparison logic, and failure detection and reporting logic.
• Build clean register and bus-connected interfaces, for example APB, AHB, or AXI-lite based control and status paths, to enable firmware interaction and subsystem integration.
• Develop testbenches, assertions, checkers, and block or subsystem-level verification environments to validate controller behavior, detection logic, configuration programming, fault response, and status reporting.
• Plan and execute functional verification for normal, corner, negative, and fault-injection scenarios, with adequate coverage of critical diagnostic behaviors.
• Collaborate with analog and mixed-signal designers to create or use behavioral models, stubs, and interface abstractions for realistic verification of failure mechanisms and observability paths.
• Debug RTL and simulation issues through waveform analysis, assertion-based checks, root-cause investigation, and close interaction with integration and product teams.
• Ensure the RTL is modular, reusable, timing-aware, synthesis-friendly, and scalable for integration across multiple SoC derivatives.

SoC Integration

• Integrate custom DFT / diagnostic IP into SoC subsystems and system-level test architecture with proper consideration for clock/reset structure, interrupt handling, and status visibility.
• Work closely with SoC integration and DFT teams to ensure compatibility with system test infrastructure, production test flows, diagnostic mechanisms, and firmware control requirements.
• Support integration readiness by addressing CDC, reset interactions, timing considerations, low-power implications, and implementation handoff requirements.

Cross-Functional Collaboration

• Work closely with digital, analog, and mixed-signal design teams, DFT engineers, SoC architects, and product/test engineering teams throughout the design and validation cycle.
• Translate analog or mixed-signal failure modes into robust digital detection logic suitable for on-chip test, screening, and diagnosis.
• Contribute to technical discussions on architecture tradeoffs, observability strategy, and practical silicon debug readiness.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, with 5–7 years of relevant experience.
• Strong hands-on experience in RTL design using Verilog/SystemVerilog.
• Practical experience in RTL verification, simulation, and debugging methodologies.
• Solid understanding of ASIC / SoC design flow including coding, simulation, synthesis, and integration.
• Good foundation in digital design concepts such as FSM design, datapath design, bus protocols (AXI/AHB/APB), clock-domain handling, reset strategy, and timing considerations.
• Experience working in complex SoC environments with cross-functional teams.

Preferred Qualifications

• Experience developing control, monitoring, or diagnostic IP associated with analog or mixed-signal subsystems.
• Exposure to behavioral modeling or interface definition for analog and mixed-signal verification use cases.
• Familiarity with subsystem-level integration, production screening considerations, and silicon debug support.
• Working knowledge of scripting or automation for verification, regression, or design productivity is an advantage.

Description:

• You would be part of a dynamic digital SoC design team that develops state-of-the-art video processing, neural processing, advanced video analytics accelerators, and the entire Camera Processor SoC. You would be joining the team to explore, evaluate and define innovative design SoC architectures, to meet or exceed the technical requirements of the SoC. You would be responsible for the successful implementation of the designs in Verilog/SystemVerilog coding, metrics measurement to meet key objectives & results, and follow-through in comprehensive verifications to successful silicon.

Requirements:

• Experience in SoC architecture and design, and RTL coding with Verilog/SystemVerilog
• Experience in ARM or RISC-V processor system
• Experience in embedded C and assembly code programming
• Experience in analysis of power, timing and area
• Experience in at least one of scripting languages (e.g. Perl, Python, TCL, or Bash)
• Disciplined, quality-minded, and highly driven for excellence
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience
• Experience in always-on system, automotive system, secured system, bus interconnect, neural processing, video processing and video analytics is a plus
• Experience in system modelling and simulation using emulator and SystemC is a plus
• Experience in UVM verification methodology is a plus
• Passionate and strong in general programming is a plus

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The role of a High Bandwidth Memory (HBM) System Engineer at Micron Technology, Inc. is pivotal in the introduction of Micron's HBM with our customers.  This role will empower customers through the utilization of High Bandwidth Memory (HBM) integrated with ground breaking 2.5D and 3D System in Package (SiP) solutions. This encompasses a comprehensive approach to system level testing, encompassing electrical, software, and system validation perspectives. The incumbent will spearhead the development of innovative test algorithms and plans, which includes the design and execution of robust system test infrastructure capabilities to ensure the highest standards of quality and performance.  Your strategic leadership will be crucial in synchronizing efforts across various teams to achieve a seamless and successful product launch with our customers.

Responsibilities:

Provide Technical Leadership and Direction

• Initiate collaborations with customers, Technology Development (TD), Testing, and Manufacturing teams in advance of silicon arrival

• Maintain responsibility for the successful customer launch of the product

• Great communication and presentation skills – ability to present to both internal leadership and customer forums

• Strong interpersonal skills with ability to convey sophisticated technical concepts to peers and customers

• Develop, diagnose, and validate HBM System testing programs and inhouse system solutions

• Assess and determine the necessary equipment and hardware for optimal system validation processes

• Lead the development of High-Performance Computing (HPC) and Artificial Intelligence (AI) software testing strategies to enhance product testing

• Strategically plan projects and manage resource allocation to adhere to established timelines and objectives

• Enhance efficiency, coverage, turnaround time of validation activities

• Provide guidance and ensure alignment with specific company-wide projects

Minimum Qualifications:

• BS or MS in Electrical or Computer Engineering or related field.

• 8+ years (BS) or 10+ years (MS) of relevant experience.

• Deep knowledge of DRAM operation, JEDEC specs, and HBM product family.

• Strong communication skills to convey complex technical concepts.

• Experience with scripting languages (Python, TCL, Perl).

• Proven innovation and problem-solving in high-performance memory development

• Good understanding of computer architecture, memory subsystems, and memory technologies

• Proven team leader – respect, integrity, positive demeanor

Preferred Qualifications:

• Understanding of system architectures and memory subsystems; Previous experience validating products with both hardware/firmware/software components

• Experience with bring-up and validation of ASIC/GPU with HBM memory subsystems

• Familiarity with industry-standard memory interfaces and protocols, such as LPDDR, DDR, HBM, GDDR, CXL, UCIe, and PCIe

• Excellent problem-solving and analytical skills

• A self-motivated, enthusiastic team player who enjoys working with others

• Good communication skills with the ability to convey complex technical concepts to other design and verification peers in verbal and written form

JOB DESCRIPTION

In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition

• Develop detailed module level and SoC level testplans for all the functional features, based on the design spec.

• Develop ASIC verification environment including all the respective components such as stimulus, checkers, assertions, monitors and scoreboards.

• Develop directed and constrain-random verification functional tests and simulate using EDA tools to verify functional spec is working

• Execute verification plans, including design bring-up, DV bring-up, regression enabling for all the features.

• Collaborate with digital design team to debug functional testcases and deliver functionally correct designs

The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment

JOB REQUIREMENTS

· BSEE or MSEE, entry level

· Strong communication, analytical and documentation skills and ability to interface with other groups

· Strong VLSI functional verification experience, preferably with exposure to complex, high speed custom VLSI products

· Strong hardware functional verification language and Object-oriental language development skill. Prefer with SystemVerilog/ UVM experience

· Familiar with ASIC verification methodology, tools, and development flow

· Working experience or familiar with Ethernet L2/L3 switch/router, SOC, AMBA bus, high-speed IO (USB-2/3, PCIe gen2/3, SATA), Flash controller, or CPU peripherals

Responsibilities:

• Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design.
• Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance.
• Develop reusable testbenches, test cases using constrained-random and directed methods, and verification modules for both block and system levels.
• Create a regression strategy, methodology, and scripting tools, ensuring comprehensive function coverage and addressing verification gaps before design releases and tape-out.
• Collaborate with design engineers to troubleshoot and resolve simulation issues.
• Provide support to test engineers during post-silicon validation.
• Mentor and guide team members and junior engineers, aiming to enhance verification efficiency.​

Requirements:

• Master in Electrical Engineering or equivalent with 8 years of relevant working experience/ PhD in Electrical Engineering or equivalent with 3 years working experience.
• Extensive understanding of UVM/OVM, Semiformal Verification, assertion-based verification, and hardware-software co-verification methodology.
• Skilled in Verilog, SystemVerilog, Python, Perl, TCL, Shell scripting, C/C++, SystemC, and assembly coding for industry-standard ISAs.
• Familiar with MIPI, AMBA (APB/AHB/AXI) bus protocols, RISC-V/ARM, or DSP cores.
• Experience in verifying designs at RTL and post-P&R gate levels.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact win@hkmsvs.com for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Position Overview:

• As a design verification engineer, you will be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space.

Requirements:

• Experience in UVM verification methodology
• Disciplined, quality-minded, and highly driven for excellence,
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience, but are open to fresh graduates with outstanding results
• Candidates with relevant experiences would be offered as Staff or Sr. Staff, taking on higher responsibilities
• Experience in video processing and video analytics is a plus
• Passionate and strong in general programming is a plus

Responsibilities:

1. Develop design requirements for an NPU based on system-level specifications.
2. Being part of modelling the performance of the NPU module and its data transaction throughput.
3. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU.
4. Understanding the mathematics of different convolution operators including different arithmetic formats (fixed point and floating point)
5. Estimate, measure and optimize PPA (Performance / Power / Area) to meet key objectives and results.
6. Optimizing micro-architecture design for low power and area is required.
7. Work closely with verification engineers to ensure comprehensive testing and debug any issues.
8. Support integration into the overall system, conducting design checks, and addressing lint/timing/CDC issues.
9. Collaborate with software teams to assist in compiler and toolchain development and their debugging.
10. Produce clear and concise design documentation.

Requirements

1. 8+ years of digital design with at least 2 to 3 years of SoC design experience is preferred.
2. At least one cycle of NPU design completion experience is required.
3. Hands on experience in digital design is a must.
4. Preferably has lead a team of at least 3 to 4 people in the past at the capacity of a design lead.
5. Experience in microarchitecture design, and RTL coding with Verilog/ System-Verilog.
6. Experience in synthesis, with analysis of power, timing and area.
7. Disciplined, quality-minded, and highly driven for excellence.
8. Excellent team player and good communication skills.
9. MSEE/BSEE in Electrical Engineering or Computer Engineering.
10. Understanding of convolution operator and number system is required.
11. Candidates with relevant experiences would be offered as Senior, taking on higher responsibilities.
12. Experience in UVM verification methodology is a plus.
13. A plus to have SoC design experience.
14. Experience with optimizing micro-architectures for low-power and low-area is a plus.
15. Knowledge in deep learning algorithms such as CNN / Transformer is a plus.
16. Experience with past design experience with NPU / GPU / DSP design is a plus.
17. Experience with ARM or RISC-V processor systems is a plus.
18. Passionate and strong in general programming is a plus.

Description:

• You would be part of a dynamic digital SoC design team that develops state-of-the-art video processing, neural processing, advanced video analytics accelerators, and the entire Camera Processor SoC. You would be joining the team to explore, evaluate and define innovative design SoC architectures, to meet or exceed the technical requirements of the SoC. You would be responsible for the successful implementation of the designs in Verilog/SystemVerilog coding, metrics measurement to meet key objectives & results, and follow-through in comprehensive verifications to successful silicon.

Requirements:

• Experience in SoC architecture and design, and RTL coding with Verilog/SystemVerilog
• Experience in ARM or RISC-V processor system
• Experience in embedded C and assembly code programming
• Experience in analysis of power, timing and area
• Experience in at least one of scripting languages (e.g. Perl, Python, TCL, or Bash)
• Disciplined, quality-minded, and highly driven for excellence
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience
• Experience in always-on system, automotive system, secured system, bus interconnect, neural processing, video processing and video analytics is a plus
• Experience in system modelling and simulation using emulator and SystemC is a plus
• Experience in UVM verification methodology is a plus
• Passionate and strong in general programming is a plus

Good Pay + Good Bonus ( 5 Days Work Week )

Junior / Entry Level / No experience / Senior Welcome apply / Full Training Provided

Work location : Woodlands & Bedok ( X2 Role )

JOB SCOPE
1.0 Design, test, debug and commission the company’s product, which include jigs and
fixtures, customized semi and fully automatic machines.
2.0 Attend meetings with customers to discuss on their requirements in new projects
and/or project proposals.
3.0 Research and develop new ideas and concept to enhance company’s performance and
competitiveness in the field of industrial automation.
4.0 Procure and/or assist in the procurement of necessary items to enable the
performance of above duties.

Requirements
1.0 Minimum ITE, Diploma or Degree in Mechanical Engineering
2.0 Minimum two years experience in customized Automation Machine Design.
3.0 Experience in customized semi-con/ connector/ machine design preferred.

Good Pay + Good allowance + Good Bonus

Interested candidates please send an updated Resume / CV in Ms Word format to lilian@recruitflash.com or WhatsApp’s your resume to 98332779 ( no Calls)

Consultant in-charge : Quah Li Lian (Lilian) ( Registration No: R1983286 )

Position Overview:

• As a design verification engineer, you will be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space.

Requirements:

• Experience in UVM verification methodology
• Disciplined, quality-minded, and highly driven for excellence,
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience, but are open to fresh graduates with outstanding results
• Candidates with relevant experiences would be offered as Senior or Staff, taking on higher responsibilities
• Experience in video processing and video analytics is a plus
• Passionate and strong in general programming is a plus

Design Engineer (Civil & Structural) - LTA Project

• Industry: A1 Main Contractor - Korean MNC
• Office is near Jurong East MRT, Singapore
• Site is at Jurong East MRT
• 5.5 Days 8am-6pm / 8am-12pm
• Salary: $3,500 - $6,000 + Bonus

Summary

• We are seeking an experienced Design Engineer (Civil & Structural) to support major LTA MRT projects, work closely with the Design Manager and project teams to ensure timely, accurate, and compliant design throughout the project lifecycle.

Job Description

• Assist the Design Manager and oversee the overall progress of design works on site.
• Manage drawing submission schedules in line with planned construction progress.
• Coordinate and review all design matters with LTA, authorities, consultants, and subcontractors.
• Provide technical solutions and offer design advice to internal teams.
• Manage and control design deliverables related to BIM, Technical, contractual, and cost requirements.
• Review subcontractors' shop drawings to ensure compliance with the design specifications and project standards.

Requirements

• Degree in Civil Engineering or related discipline.
• Minimum 5 years of engineering experience.
• At least 3 years of experience in civil & structural or architectural design for LTA MRT projects.

Cheong Yeat Long | R25145358

The Supreme HR Advisory Pte Ltd | EA 14C7279

As a Scanner Engineer in the Front‑End (FE) Operation Central Team (OCT) Central Process & Equipment Engineering (CPEE) Photo Scanner group, you will provide deep technical and operational leadership to drive best‑in‑class photo scanner performance across the global Micron network. 

You will partner closely with Technology Development (TD), R&D, manufacturing sites, suppliers, and central planning to deliver improvements in scanner uptime, utilization, productivity (WPD), tool install readiness, MA%, cost, and quality.

You will serve as a domain expert in scanner engineering, technology introduction, and network benchmarking, ensuring consistent execution and continuous improvement across sites. You will influence and elevate Micron’s global Photo Scanner performance, working with world‑class engineers, suppliers, and partner teams. This role offers a mix of deep technical challenges, cross‑site leadership, and large‑scale impact across the global network.

Key Responsibilities

1. Scanner Performance & Productivity Leadership

• Drive global improvements in WPD, uptime, utilization, MA%, and tool throughput across the Micron photo network.

• Benchmark site performance and establish best‑known‑methods (BKMs) to reduce variability and elevate network standards.

• Lead assessments and recovery actions for recurring issues, chronic network bottlenecks, and tool performance gaps.

2. New Technology & Tool Install Introduction

• Collaborate with TD, suppliers, and global facilities/layout teams to optimize tool‑install sequencing, qualification, ramp models, and readiness.

• Provide technical leadership during first‑of‑kind workstation introductions, ensuring manufacturing availability and utilization meet targets.

• Govern technical change management, ensuring alignment and consistency across sites.

3. Cross‑Functional and Supplier Collaboration

• Work with PEE teams, Quality Engineering, Central Planning, Procurement, and external suppliers to resolve issues and drive engineering improvements.

• Support supplier engagements, quality workshops, and cross‑company collaboration (e.g., ASML x Micron workshops) to ensure strong integration and performance stewardship. 

4. Continuous Improvement & Cost Optimization

• Lead projects targeting tool performances and availability, and cycle‑time improvements.

• Prioritize and execute continuous improvement projects aligned to OCT/CPEE strategies and manufacturing needs.

• Evaluate technical and operational solutions to reduce downtime, technician labor demand, and material/scrap cost.

5. Network Governance & Technical Stewardship

• Provide expert guidance on TOR, BKM governance, process windows, and technical decision frameworks.

• Ensure standardization of troubleshooting flows, tool health metrics, and scanner capability indices across sites.

Minimum Qualifications

• Bachelor’s or Master’s degree in Engineering (Electrical, Mechanical, Physics, Materials, or related field).

• 6+ years of relevant semiconductor photo processing or scanner engineering experience.

• Excellent communication and collaboration skills, including supplier engagement.

• Strong expertise with scanner hardware, applications, diagnostics, and process‑equipment interaction.

• Proven ability to lead cross‑functional and cross‑site engineering initiatives.

Preferred Qualifications

• Experience with ASML scanners and advanced technology node ramps.

• Demonstrated success in driving large‑scale manufacturing or equipment performance programs.

• Technical leadership in Photo technical engineering functions with excellent project management knowledge

• Experience with structured problem solving (8D, DOE, SPC).
  

  Maximizes yield by working on tools, the process, or wafer fabrication recipes. Troubleshoots wafer fabrication problems and performs root cause analysis. Works with other process areas to understand and control process deviations. Long-term investigation of defect issues may require extensive work with shift engineering and other functional areas. Evaluates products to ensure they meet the required design and performance specifications. Conducts research to assess process adjustment requirements and recommends process improvements or equipment changes needed to efficiently manufacture new product or part types.